公开(公告)号：US20080090308A1

公开(公告)日：2008-04-17

申请号：US11998085

申请日：2007-11-28

申请人： Takafumi Noda ,  Hiroshi Fukuda

发明人： Takafumi Noda ,  Hiroshi Fukuda

IPC分类号： H01L21/8239

CPC分类号： H01L23/544 ,  G03F9/7076 ,  H01L27/11502 ,  H01L27/11507 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer, and an oxidation barrier layer provided on the conductive layer, wherein an area occupancy ratio of the recessed section in the plane pattern is 5% or greater.

摘要翻译： 提供了半导体器件的对准标记。 对准标记限定了平面图案，并且包括嵌入在设置在绝缘层中的凹部中的导电层和设置在导电层上的氧化阻挡层，其中平面图案中凹部的面积占有率为5％ 或更大。

公开(公告)号：US20060220265A1

公开(公告)日：2006-10-05

申请号：US11389997

申请日：2006-03-27

申请人： Takafumi Noda ,  Hiroshi Fukuda

发明人： Takafumi Noda ,  Hiroshi Fukuda

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  G03F9/7076 ,  H01L27/11502 ,  H01L27/11507 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer, and an oxidation barrier layer provided on the conductive layer, wherein an area occupancy ratio of the recessed section in the plane pattern is 5% or greater.

摘要翻译： 提供了半导体器件的对准标记。 对准标记限定了平面图案，并且包括嵌入在设置在绝缘层中的凹部中的导电层和设置在导电层上的氧化阻挡层，其中平面图案中凹部的面积占有率为5％ 或更大。

公开(公告)号：US08736010B2

公开(公告)日：2014-05-27

申请号：US13166937

申请日：2011-06-23

申请人： Takafumi Noda

发明人： Takafumi Noda

IPC分类号： H01L31/058

CPC分类号： G01J5/34

摘要： A pyroelectric detector includes a pyroelectric detection element, a support member, and a support part. The pyroelectric detection element has a capacitor including a first electrode, a second electrode, and a pyroelectric body disposed between the first and second electrodes, and a first reducing gas barrier layer that protects the capacitor from reducing gas. The support member includes first and second sides with the pyroelectric detection element being mounted on the first side and the second side facing a cavity. The support member has a mounting member on which the capacitor is mounted and an arm member linked to the mounting member. The support part supports a portion of the support member. An outer peripheral edge of the first reducing gas barrier layer is disposed between and spaced apart from an outer peripheral edge of the mounting member and an outer peripheral edge of the capacitor in plan view.

摘要翻译： 热电检测器包括热电检测元件，支撑元件和支撑部件。 热电检测元件具有包括第一电极，第二电极和布置在第一和第二电极之间的热电体的电容器，以及保护电容器免于还原气体的第一还原气体阻挡层。 支撑构件包括第一和第二侧，其中热电检测元件安装在第一侧上，第二侧面向空腔。 支撑构件具有其上安装有电容器的安装构件和连接到安装构件的臂构件。 支撑部分支撑支撑构件的一部分。 第一还原性气体阻隔层的外周缘设置在安装构件的外周边缘之间并且与平面图中的电容器的外周边缘隔开。

公开(公告)号：US08592937B2

公开(公告)日：2013-11-26

申请号：US13371648

申请日：2012-02-13

申请人： Takafumi Noda

发明人： Takafumi Noda

IPC分类号： H01L35/00

CPC分类号： G01J5/023 ,  G01J5/024 ,  G01J5/0285 ,  G01J5/34

摘要： A pyroelectric detector includes a substrate, a support member and a pyroelectric detection element, which includes a capacitor, first and second reducing gas barrier layers, an insulating layer, a plug and a second electrode wiring layer. The first reducing gas barrier layer covers at least a second electrode and a pyroelectric body of the capacitor, and has a first opening that overlaps the second electrode in plan view. The insulating layer covers at least the first reducing gas barrier layer, and has a second opening that overlaps the first opening in plan view. The plug is disposed in the first and second openings and connected to the second electrode. The second electrode wiring layer is formed on the insulating layer and connected to the plug. The second reducing gas barrier layer is formed on the insulating layer and the second electrode wiring layer and covers at least the plug.

摘要翻译： 热电检测器包括基板，支撑构件和热电检测元件，其包括电容器，第一和第二还原气体阻挡层，绝缘层，插塞和第二电极布线层。 第一还原气体阻隔层覆盖电容器的至少第二电极和热电体，并且在俯视图中具有与第二电极重叠的第一开口。 绝缘层至少覆盖第一还原性气体阻隔层，并且在平面图中具有与第一开口重叠的第二开口。 插头设置在第一和第二开口中并连接到第二电极。 第二电极布线层形成在绝缘层上并与插头连接。 第二还原气体阻隔层形成在绝缘层和第二电极布线层上并且至少覆盖该插塞。

公开(公告)号：US07825027B2

公开(公告)日：2010-11-02

申请号：US12271364

申请日：2008-11-14

申请人： Takafumi Noda ,  Toshihiko Higuchi

发明人： Takafumi Noda ,  Toshihiko Higuchi

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L28/55 ,  H01L27/11509

摘要： A method for manufacturing a memory device including a ferroelectric memory array region and a logic circuit region is provided. The method includes the steps of: forming, above a base substrate, a plurality of ferroelectric capacitors in the ferroelectric memory array region; forming a wiring layer above the base substrate in the logic circuit region; forming an interlayer dielectric layer that covers the ferroelectric capacitors and the wiring layer; etching the interlayer dielectric layer formed at least in the ferroelectric memory array region to form a concave section; polishing the interlayer dielectric layer by a CMP (chemical mechanical polishing) method; etching the interlayer dielectric layer above the ferroelectric capacitors and the wiring layer to form contact holes; and forming contact sections in the contact holes.

摘要翻译： 提供了一种制造包括铁电存储器阵列区域和逻辑电路区域的存储器件的方法。 该方法包括以下步骤：在基底基板上形成铁电存储器阵列区域中的多个铁电电容器; 在逻辑电路区域中的基底基板上形成布线层; 形成覆盖所述铁电电容器和所述布线层的层间绝缘膜; 蚀刻至少形成在铁电存储器阵列区域中的层间电介质层，以形成凹部; 通过CMP（化学机械抛光）方法对层间绝缘层进行抛光; 蚀刻铁电电容器和布线层上方的层间电介质层，形成接触孔; 以及在接触孔中形成接触部分。

公开(公告)号：US20090072287A1

公开(公告)日：2009-03-19

申请号：US12192172

申请日：2008-08-15

申请人： Takafumi Noda

发明人： Takafumi Noda

IPC分类号： H01L21/02 ,  H01L27/11

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/57

摘要： A semiconductor device includes: a ferroelectric capacitor including a first electrode provided above a substrate, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a hydrogen barrier film that covers a top surface and a side surface of the ferroelectric capacitor; an interlayer dielectric film that covers the ferroelectric capacitor and the substrate; a contact hole that penetrates the interlayer dielectric film and the hydrogen barrier film and exposes the second electrode; a barrier metal that covers a top surface of the second electrode exposed in the contact hole and an inner wall surface of the contact hole and is composed of a conductive material having hydrogen barrier property; and a plug conductive section that is embedded in the contact hole and conductively connects to the barrier metal, wherein the inner wall surface of the contact hole at the hydrogen barrier film includes a concave curved surface facing the interior of the contact hole, and the contact hole at the hydrogen barrier film has an inner diameter that gradually becomes smaller toward the second electrode.

摘要翻译： 半导体器件包括：强电介质电容器，包括设置在衬底上的第一电极，设置在第一电极上的铁电体膜和设置在铁电体膜上的第二电极; 覆盖所述强电介质电容器的顶面和侧面的氢阻挡膜; 覆盖铁电电容器和基板的层间绝缘膜; 穿过所述层间电介质膜和所述氢阻挡膜并使所述第二电极露出的接触孔; 覆盖暴露在接触孔中的第二电极的顶表面和接触孔的内壁表面的阻挡金属，并且由具有氢阻挡性的导电材料构成; 以及嵌入在所述接触孔中并与所述阻挡金属导电连接的插头导电部，其中，所述氢阻挡膜的所述接触孔的内壁面包括面向所述接触孔的内部的凹曲面， 氢阻挡膜的孔的内径朝向第二电极逐渐变小。

公开(公告)号：US07163855B2

公开(公告)日：2007-01-16

申请号：US10902699

申请日：2004-07-29

申请人： Takafumi Noda ,  Masahiro Hayashi ,  Akihiko Ebina ,  Masahiko Tsuyuki

发明人： Takafumi Noda ,  Masahiro Hayashi ,  Akihiko Ebina ,  Masahiko Tsuyuki

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823892 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/0928

摘要： A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving transistor forming region.

摘要翻译： 提供一种半导体器件制造方法，包括：在半导体层中形成在高击穿电压晶体管形成区域中成为第一阱的第一杂质层; 形成成为所述高击穿电压晶体管形成区域的偏移区域的第二杂质层; 通过热处理所述半导体层来扩散所述第一和第二杂质层的杂质来形成所述第一阱和所述偏移区域; 在形成第一阱和偏移区之后，通过沟槽元件隔离方法在半导体层中形成元件隔离区; 在高击穿电压晶体管形成区域中形成第一栅极电介质层; 在半导体层中的低电压驱动晶体管形成区域中形成第二阱; 在所述低电压驱动晶体管形成区域中形成第二栅极电介质层; 以及在高击穿电压晶体管形成区域和低电压驱动晶体管形成区域中形成栅电极。

公开(公告)号：US07001812B2

公开(公告)日：2006-02-21

申请号：US10961768

申请日：2004-10-07

申请人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

发明人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

IPC分类号： H01L21/8234

CPC分类号： H01L27/11526 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/11546

摘要： A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.

摘要翻译： 一种半导体器件的制造方法，其在同一半导体层上具有不同的高压栅极的晶体管以及高电压漏极和MNOS存储晶体管。

公开(公告)号：US20050118759A1

公开(公告)日：2005-06-02

申请号：US10962111

申请日：2004-10-07

申请人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

发明人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

IPC分类号： H01L21/283 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823814

摘要： A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.

摘要翻译： 制造其半导体器件的方法包括在同一半导体层中，其晶体管和MNOS型存储晶体管具有不同的栅极耐受电压和漏极耐受电压。

公开(公告)号：US08569698B2

公开(公告)日：2013-10-29

申请号：US13186775

申请日：2011-07-20

申请人： Jun Takizawa ,  Takafumi Noda ,  Taketomi Kamikawa ,  Mitsuhiro Yamamura

发明人： Jun Takizawa ,  Takafumi Noda ,  Taketomi Kamikawa ,  Mitsuhiro Yamamura

IPC分类号： G01J5/00

CPC分类号： G01J5/10 ,  G01J5/08 ,  G01J5/0853 ,  G01J5/34

摘要： A thermal detector has a thermal detection element in which a physical characteristic changes based on temperature, a light-absorbing member configured and arranged to collect heat and transmit collected heat to the thermal detection element, a support member mounting the thermal detection element on a first side with a second surface facing a cavity, and a support part supporting a portion of the support member. The light-absorbing member is a plate shaped member at least partially contacting a top part of the thermal detection element and having a portion overhanging to an outside from the top part of the thermal detection element in plan view.

摘要翻译： 热检测器具有物理特性基于温度而变化的热检测元件，构造并布置成收集热量并将收集的热量传递到热检测元件的光吸收构件;将热检测元件安装在第一 侧面具有面向空腔的第二表面和支撑所述支撑构件的一部分的支撑部分。 光吸收构件是平板状的板状构件，其至少部分地接触热检测元件的顶部并具有从热检测元件的顶部向外伸出的部分。