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    Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line
    1.
    发明授权
    Semiconductor integrated circuit device having input/output buffer cells each comprising a plurality of transistor regions arranged in a single line 失效
    具有输入/输出缓冲单元的半导体集成电路器件，每个单元包括排列成一行的多个晶体管区域

    公开(公告)号：US4992845A

    公开(公告)日：1991-02-12

    申请号：US294020

    申请日：1989-01-06

    申请人： Takahiko Arakawa ,  Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Ichiro Tomioka ,  Masahiro Ueda ,  Yoshihiro Okuno

    发明人： Takahiko Arakawa ,  Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Ichiro Tomioka ,  Masahiro Ueda ,  Yoshihiro Okuno

    IPC分类号： H01L21/82 ,  H01L27/118

    CPC分类号： H01L27/11898

    摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).

    摘要翻译： 在半导体芯片（1）的中央部分设置有内部逻辑门部（3），设置有用于包围内部逻辑门部（3）的输入/输出缓冲器（4），并且提供接合焊盘（2） 在对应于输入/输出缓冲器中的输入/输出缓冲单元（5）的半导体芯片（1）的外围部分中。 每个输入/输出缓冲器单元（5）包括输出P-MOS部分（6），输出N-MOS部分（7），输入/逻辑P-MOS部分（8）和输入/ MOS部分（9），它们在从接合焊盘（2）到内部逻辑门部分（3）的方向上分别布置成单行。 在上述结构中，键合焊盘（2）的焊盘布置方向上的输入/输出缓冲单元（5）中的每一个的尺寸减小，从而可以根据 减少每个输入/输出缓冲单元（5）所需的排列方向的空间的使用。

    Semiconductor integrated circuit device having rest function
    2.
    发明授权
    Semiconductor integrated circuit device having rest function 失效
    具有休息功能的半导体集成电路器件

    公开(公告)号：US4780666A

    公开(公告)日：1988-10-25

    申请号：US81256

    申请日：1987-08-03

    申请人： Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Ichiro Tomioka ,  Takahiko Arakawa

    发明人： Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Ichiro Tomioka ,  Takahiko Arakawa

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G11C19/28 ,  G01R15/12

    CPC分类号： G01R31/318541

    摘要： A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.

    摘要翻译： 半导体集成电路器件包括设置在相邻电路块之间的多个锁存电路。 每个锁存电路用于在电路设备的正常操作期间将来自前一电路块的输出数据直接传送到后续电路块，以保持输出数据直到扫描相关扫描寄存器并将其提供给后续电路块 扫描模式，并且在测试操作的测试模式中与外部时钟同步地输出输出数据。

    Semiconductor intergrated circuit device
    3.
    发明授权
    Semiconductor intergrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US4870345A

    公开(公告)日：1989-09-26

    申请号：US81095

    申请日：1987-08-03

    申请人： Ichiro Tomioka ,  Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Takahiko Arakawa

    发明人： Ichiro Tomioka ,  Kazuhiro Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi ,  Takahiko Arakawa

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318536

    摘要： A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.

    摘要翻译： 半导体集成电路包括级联异步顺序逻辑电路。 在异步时序电路之间提供扫描移位寄存器，以允许将测试数据应用于电路的输入，并根据测试数据锁存和移出由电路提供的输出数据。 在扫描移位寄存器和异步顺序电路的输入之间提供附加的选通电路，以防止锁存在扫描移位寄存器中的新数据使测试期间连接到扫描移位寄存器输出的异步时序电路变化。 可以使用相同的附加电路来响应于外部产生的门控控制信号来提供受控宽度和/或定时到异步顺序电路输入的脉冲。

    Inverter circuit
    5.
    发明授权
    Inverter circuit 失效
    逆变电路

    公开(公告)号：US4916385A

    公开(公告)日：1990-04-10

    申请号：US262302

    申请日：1988-10-25

    申请人： Ichiro Tomioka ,  Masahiro Ueda ,  Takahiko Arakawa ,  Toshiaki Hanibuchi ,  Yoshihiro Okuno

    发明人： Ichiro Tomioka ,  Masahiro Ueda ,  Takahiko Arakawa ,  Toshiaki Hanibuchi ,  Yoshihiro Okuno

    IPC分类号： G01R19/165 ,  G01R31/316 ,  G01R31/317 ,  G01R31/319 ,  H03K17/00 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0948

    CPC分类号： H03K19/00361 ,  G01R31/316 ,  G01R31/31905

    摘要： An inverter circuit (I.sub.3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (V.sub.DD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (T.sub.E). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.

    摘要翻译： 公开了一种逆变器电路（I3），其包括串联连接在电源（VDD）和地（GND）之间的P沟道MOSFET（3）和N沟道MOSFET（4）。 逆变器电路还包括在FET（3）和（4）的栅极之间并联连接的P沟道MOSFET（5）和N沟道MOSFET（6）。 FET（3）和（4）的栅极连接以接收测试模式信号（TE）。 在测试模式操作中，使FET（6）导通以允许通过FET（6）将输入信号施加到FET（4）的栅极。 响应于通过FET（6）施加的输出信号，具有低于FET（3）的导通电阻的FET（4）被驱动成导通，从而提供缓慢上升的输出信号。 缓慢上升的输出信号没有下冲或振铃。

    Neural network integrated circuit device having self-organizing function
    6.
    发明授权
    Neural network integrated circuit device having self-organizing function 失效
    具有自组织功能的神经网络集成电路器件

    公开(公告)号：US5148514A

    公开(公告)日：1992-09-15

    申请号：US515476

    申请日：1990-04-24

    申请人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

    发明人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

    IPC分类号： G06N3/063

    CPC分类号： G06N3/063

    摘要： An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix to form a rectangle including a first and second triangles on a semiconductor chip, a plurality of neuron representing units and a plurality of educator signal control circuits which are arranged along first and second sides of the rectangle, and a plurality of buffer circuits arranged along third and fourth sides of the rectangle. The first side is opposite to the third side, and the second side is opposite to the fourth side. Axon signal transfer lines and dendrite signal lines are so arranged that the neuron representing units are full-connected in each of the first right triangle the second right triangle. Alternatively, axon signal lines and dendrite signal ines are arranged in parallel with rows and columns of the synapse representing unit matrix, so that the neuron representing units are full-connected in the rectangle. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines.

    摘要翻译： 具有Boltzmann模型学习功能的延伸定向集成电路装置包括多个突触，其表示以矩阵排列的单元，以形成包括半导体芯片上的第一和第二三角形的矩形，多个神经元表示单元和多个 沿矩形的第一和第二侧布置的教育者信号控制电路以及沿矩形的第三和第四侧布置的多个缓冲电路。 第一面与第三面相反，第二面与第四面相反。 轴突信号传输线和枝晶信号线被布置成使得表示单元的神经元在第二直角三角形的第一直角三角形的每一个中是全连接的。 或者，轴突信号线和枝晶信号与突触表示单位矩阵的行和列平行布置，使得表示单元的神经元表示在矩形中。 每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。

    Neural network integrated circuit device having self-organizing function
    7.
    发明授权
    Neural network integrated circuit device having self-organizing function 失效
    具有自组织功能的神经网络集成电路器件

    公开(公告)号：US5293457A

    公开(公告)日：1994-03-08

    申请号：US877514

    申请日：1992-05-01

    申请人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

    发明人： Yutaka Arima ,  Ichiro Tomioka ,  Toshiaki Hanibuchi

    IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/063 ,  G06N99/00 ,  H01L21/822 ,  H01L27/04 ,  G06F7/00

    CPC分类号： G06N3/063

    摘要： An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix, a plurality of neuron representing units, a plurality of educator signal control circuits, and a plurality of buffer circuits. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines. Each synapse representing unit includes a learning control circuit which derives synapse load change value data in accordance with predetermined learning rules in response to a first axon signal Si and a second axon signal Sj, a synapse load representing circuit which corrects a synapse load in response to the synapse load change valued data and holds the corrected synapse load value Wij, a first synapse coupling operating circuit which derives a current signal indicating a product Wij.multidot.Si from the synapse load Wij and the first axon signal Si and transfers the same to a first dendrite signal line, and a second product signal indicating a product Wij.multidot.Sj from the synapse load Wij and the second axon signal Sj and transfers the same onto a second dendrite signal line.

    摘要翻译： 具有Boltzmann模型学习功能的延伸定向集成电路器件包括表示以矩阵排列的单元的多个突触，多个神经元表示单元，多个教育者信号控制电路和多个缓冲电路。 每个突触代表单元连接到一对轴突信号传输线和一对枝晶信号传输线。 每个突触表示单元包括学习控制电路，该学习控制电路响应于第一轴突信号Si和第二轴突信号Sj，根据预定的学习规则导出突触负荷变化值数据，突变负载表示电路响应于 突触负荷改变数值数据并保持校正的突触负载值Wij，第一突触耦合操作电路从突触负载Wij和第一轴突信号Si导出指示产品Wij * Si的电流信号，并将其转移到第一 枝晶信号线和第二产品信号，其从突触载荷Wij和第二轴突信号Sj指示乘积Wij * Sj，并将其传送到第二枝晶信号线。

    Semiconductor logic integrated circuit device having first and second operation modes for testing
    8.
    发明授权
    Semiconductor logic integrated circuit device having first and second operation modes for testing 失效
    具有用于测试的第一和第二操作模式的半导体逻辑集成电路器件

    公开(公告)号：US4825439A

    公开(公告)日：1989-04-25

    申请号：US86447

    申请日：1987-08-18

    申请人： Kazuhior Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi

    发明人： Kazuhior Sakashita ,  Satoru Kishida ,  Toshiaki Hanibuchi

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C19/28 ,  H03K19/003

    CPC分类号： H03K19/00346 ,  G01R31/318541

    摘要： A semiconductor logic integrated circuit device comprising a signal selection means and a storing means, which is capable of adjusting the logic levels of an output signal therefrom. With such a circuit device, the signal selection means and the storing means are controlled in normal operation mode so that a parallel input signal is allowed to be output as a parallel output signal from output terminals of the circuit device after subjecting the parallel input signal to logical signal processing. On the other hand, the signal selection means and the storing means are controlled in a testing opertion mode so that the parallel input signal are output in serial mode from a serial signal output terminal of the circuit device, and a serial input signal to the signal selection means is allowed to be stored in the storing means to adjust the logic levels of the output signal from the circuit device at desired levels voluntarily.

    摘要翻译： 一种包括信号选择装置和存储装置的半导体逻辑集成电路装置，其能够调节其输出信号的逻辑电平。 利用这样的电路装置，信号选择装置和存储装置在正常工作模式下被控制，从而允许并行输入信号作为来自电路装置的输出端的并行输出信号输出， 逻辑信号处理。 另一方面，信号选择装置和存储装置被控制在测试操作模式中，使得并行输入信号以串行模式从电路装置的串行信号输出端输出，并将串行输入信号输出到信号 选择装置被允许存储在存储装置中，以自愿地将电路装置的输出信号的逻辑电平调整到所希望的电平。

    ECL integrated circuit allowing fast operation
    9.
    发明授权
    ECL integrated circuit allowing fast operation 失效
    ECL集成电路允许快速操作

    公开(公告)号：US5574391A

    公开(公告)日：1996-11-12

    申请号：US453120

    申请日：1995-05-30

    申请人： Toshiaki Hanibuchi ,  Yasushi Hayakawa ,  Masahiro Ueda

    发明人： Toshiaki Hanibuchi ,  Yasushi Hayakawa ,  Masahiro Ueda

    IPC分类号： H03K19/086 ,  H03K19/013

    CPC分类号： H03K19/0136

    摘要： In an ECL circuit, when a potential of an input signal A changes from "L" to "H", an output signal D correspondingly changes from "H" to "L", and, at this time, an output sent from a switching stage circuit is supplied to a gate of a PMOS transistor via a control capacitor. Thereby, a base current of a pull-down transistor flows, and change of a potential of an output terminal node is promoted. An NMOS transistor receiving the potential of the output terminal node is arranged between a node and a VEE supply terminal. Therefore, when the potential changes, the current flowing through a transistor decreases, and the base current of the pull-down transistor further increases, so that the change of the output signal D is further promoted.

    摘要翻译： 在ECL电路中，当输入信号A的电位从“L”变为“H”时，输出信号D相应地从“H”变为“L”，此时，从切换 经由控制电容器向PMOS晶体管的栅极提供级电路。 由此，下拉晶体管的基极电流流动，促进输出端子节点的电位变化。 接收输出端子节点的电位的NMOS晶体管配置在节点与VEE供电端子之间。 因此，当电位变化时，流过晶体管的电流减小，并且下拉晶体管的基极电流进一步增加，从而进一步促进输出信号D的变化。

    Bi-CMOS output buffer circuit for CMOS-to-ECL conversion
    10.
    发明授权
    Bi-CMOS output buffer circuit for CMOS-to-ECL conversion 失效
    用于CMOS到ECL转换的双CMOS输出缓冲电路

    公开(公告)号：US5561382A

    公开(公告)日：1996-10-01

    申请号：US392321

    申请日：1995-02-22

    申请人： Masahiro Ueda ,  Toshiaki Hanibuchi

    发明人： Masahiro Ueda ,  Toshiaki Hanibuchi

    IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/082

    CPC分类号： H03K19/017527 ,  H03K19/0008

    摘要： The logic of an intermediate signal (Y.sub.1) goes high when an input signal (CI) makes an "L" to "H" transition, and then a transistor (Q.sub.1) turns on and a transistor (Q.sub.2) turns off. The input signal (CI) at a potential corresponding to the logic "H" at a CMOS level has been applied to the gate of an NMOS transisitor (N.sub.1), and the NMOS transistor (N.sub.1) turns on rapidly. At this time, only current flowing through the base of an output transistor (Q.sub.0) flows through parallel connection of a resistor (R.sub.2) and an on-resistance of the NMOS transistor (N.sub.1). Since the NMOS transistor (N.sub.1) is on, the base potential of the output transistor (Q.sub.0) is raised if the resistor (R.sub.2) has a high resistance, and current fed from the output transistor (Q.sub.0) increases, thereby raising the emitter potential of the output transistor (Q.sub.0). Then the logic of an output signal (EO) goes high. Power consumption of an output buffer circuit is reduced.

    摘要翻译： 当输入信号（CI）进行“L”到“H”转换时，中间信号（Y1）的逻辑变为高电平，然后晶体管（Q1）导通，晶体管（Q2）截止。 在CMOS电平对应于逻辑“H”的电位处的输入信号（CI）被施加到NMOS截止器（N1）的栅极，并且NMOS晶体管（N1）快速导通。 此时，仅流过输出晶体管（Q0）的基极的电流流过电阻器（R2）和NMOS晶体管（N1）的导通电阻的并联连接。 由于NMOS晶体管（N1）导通，如果电阻器（R2）具有高电阻，则输出晶体管（Q0）的基极电位升高，并且从输出晶体管（Q0）馈送的电流增加，从而提高发射极电位 的输出晶体管（Q0）。 然后输出信号（EO）的逻辑变高。 输出缓冲电路的功耗降低。