公开(公告)号：US06657467B2

公开(公告)日：2003-12-02

申请号：US10216318

申请日：2002-08-12

申请人： Takahiro Seki ,  Masakatsu Nakai

发明人： Takahiro Seki ,  Masakatsu Nakai

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/135 ,  H03K5/14 ,  H03K2005/00026 ,  H03K2005/0011 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0818

摘要： The present invention provides a semiconductor device a comprising: a delayed-signal-generating circuit for delaying a reference pulse signal by a delay time caused by a delay component on a critical path of a target circuit by a selector included in the delayed signal generating circuit and, thereby, generating a delayed pulse signal; a detection-signal-generating circuit, having the same delay component as the selector, for generating a detection pulse signal delayed in phase by one cycle of a clock signal Ck with respect to the reference pulse signal; a delay-difference-detecting circuit for detecting a phase difference between the delayed pulse signal and the detection pulse signal; and a control circuit for adjusting the magnitude of a power-supply voltage VDD supplied to the target circuit according to the-phase difference detected by the delay-difference-detecting circuit.

摘要翻译： 本发明提供一种半导体器件a，包括：延迟信号发生电路，用于通过包括在延迟信号发生电路中的选择器将参考脉冲信号延迟由目标电路的关键路径上的延迟分量引起的延迟时间 从而产生延迟的脉冲信号; 检测信号发生电路，具有与选择器相同的延迟分量，用于产生相对于参考脉冲信号相位延迟一个时钟信号Ck的周期的检测脉冲信号; 延迟差检测电路，用于检测延迟脉冲信号和检测脉冲信号之间的相位差; 以及控制电路，用于根据由延迟差检测电路检测的相位差来调整提供给目标电路的电源电压VDD的大小。

公开(公告)号：US07265590B2

公开(公告)日：2007-09-04

申请号：US10713365

申请日：2003-11-14

申请人： Takahiro Seki ,  Masakatsu Nakai ,  Tetsumasa Meguro

发明人： Takahiro Seki ,  Masakatsu Nakai ,  Tetsumasa Meguro

IPC分类号： H03K5/19

CPC分类号： H03L7/0805 ,  H03K2005/00058 ,  H03L7/0814

摘要： A semiconductor apparatus for flexibly and effectively configuring a delay monitor circuit without an increase in circuit scale includes a delay signal generation circuit for switching the configuration of delay element arrays based on first configuration information and second configuration information and propagating a delay element array wherein a pulse is switched, a register group having a first register for the first configuration information and a second register for second configuration information, a selector for outputting to the delay signal generation circuit the first configuration information and second configuration information in accordance with an instruction of a selection signal in a time sharing way, and a control circuit for controlling a power source voltage based on delay information of a delay element array and outputting to the selector a selection signal to select from the first configuration information and second configuration information in a time sharing way.

摘要翻译： 一种用于在不增加电路规模的情况下灵活有效地配置延迟监视电路的半导体装置包括：延迟信号产生电路，用于根据第一配置信息和第二配置信息切换延迟元件阵列的配置，并传播延迟元件阵列，其中脉冲 被切换，具有用于第一配置信息的第一寄存器和用于第二配置信息的第二寄存器的寄存器组，选择器，用于根据选择的指令向延迟信号产生电路输出第一配置信息和第二配置信息 信号分配方式，以及控制电路，用于根据延迟元件阵列的延迟信息控制电源电压，并向选择器输出选择信号，以从第一配置信息和第二配置信息中选择时间分配w ay。

公开(公告)号：US08008733B2

公开(公告)日：2011-08-30

申请号：US12453503

申请日：2009-05-13

申请人： Masakatsu Nakai

发明人： Masakatsu Nakai

IPC分类号： H01L27/088

CPC分类号： H01L27/092 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a semiconductor device having a power cutoff transistor including a semiconductor substrate of a first conductivity type; and first and second wells of the first conductivity type formed to be spaced from each other in the semiconductor substrate.

摘要翻译： 本文公开了一种具有功率截止晶体管的半导体器件，其包括第一导电类型的半导体衬底; 并且第一导电类型的第一和第二阱形成为在半导体衬底中彼此间隔开。

公开(公告)号：US20090309170A1

公开(公告)日：2009-12-17

申请号：US12453503

申请日：2009-05-13

申请人： Masakatsu Nakai

发明人： Masakatsu Nakai

IPC分类号： H01L27/088

CPC分类号： H01L27/092 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a semiconductor device having a power cutoff transistor including a semiconductor substrate of a first conductivity type; and first and second wells of the first conductivity type formed to be spaced from each other in the semiconductor substrate.

摘要翻译： 本文公开了一种具有功率截止晶体管的半导体器件，其包括第一导电类型的半导体衬底; 并且第一导电类型的第一和第二阱形成为在半导体衬底中彼此间隔开。

公开(公告)号：US07119523B2

公开(公告)日：2006-10-10

申请号：US10806902

申请日：2004-03-23

申请人： Masakatsu Nakai

发明人： Masakatsu Nakai

IPC分类号： G05F1/40 ,  H03L7/06 ,  H02H7/10

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172

摘要： A semiconductor chip able to reduce wasteful power loss due to a margin of power supply voltage considering variation of characteristics. A voltage setting signal for setting the power supply voltage to be supplied to a target circuit is generated in a voltage controller in the semiconductor chip based on a delay time of a delay signal of a replica circuit with respect to a clock signal. The maximum value of power supply voltage set by the voltage setting signal is restricted to the maximum value of the power supply voltage determined based on variations in production of the semiconductor chip. Accordingly, even when the value of the power supply voltage set based on the delay signal exceeds the maximum value due to the margin set considering the variation of characteristics, the voltage setting of the voltage setting signal output to the external power supply is restricted to the maximum value, so wasteful power loss can be suppressed.

摘要翻译： 一种半导体芯片，考虑到特性的变化，能够减少由于电源电压的裕度造成的浪费的功率损耗。 基于复制电路相对于时钟信号的延迟信号的延迟时间，在半导体芯片中的电压控制器中产生用于设定要提供给目标电路的电源电压的电压设定信号。 由电压设定信号设定的电源电压的最大值被限制为基于半导体芯片的制造变化而确定的电源电压的最大值。 因此，即使考虑到特性的变化，由于根据延迟信号设定的电源电压的值超过最大值，所以输出到外部电源的电压设定信号的电压设定被限制为 最大值，因此可以抑制浪费的功率损耗。