公开(公告)号：US08031481B2

公开(公告)日：2011-10-04

申请号：US11818447

申请日：2007-06-13

申请人： Takahiro Shimoirisa ,  Atsumi Kawata ,  Fusaaki Kozawa

发明人： Takahiro Shimoirisa ,  Atsumi Kawata ,  Fusaaki Kozawa

IPC分类号： H05K7/14

CPC分类号： H05K1/14 ,  H05K7/1408 ,  H05K9/0062 ,  H05K2201/044 ,  H05K2201/2018

摘要： The present invention is provided a structure for mounting a printed board in which each connector that is attached to each of a plurality of sub printed boards, which are juxtaposed to one another with respect to a main printed board secured to a metal backboard, is inserted into each of a plurality of connectors that are juxtaposed to one another on the main printed board so that the sub printed boards are mounted on the main printed board by the connector connections. Parts of both ends of an area in proximity to a semiconductor-device mounted area on each of the sub printed boards ate pinched between a first metal frame and a second metal frame so that each of the sub printed boards are secured.

摘要翻译： 本发明提供了一种用于安装印刷电路板的结构，其中插入相对于固定到金属背板的主印刷板彼此并列的多个次印刷电路板中的每一个附接的每个连接器被插入 在主印刷电路板上彼此并置的多个连接器中的每一个连接器中，通过连接器连接将副印刷电路板安装在主印刷电路板上。 在每个副印刷电路板上靠近半导体器件安装区域的区域的两端的部分被夹在第一金属框架和第二金属框架之间，使得每个副印刷电路板被固定。

公开(公告)号：US20080007895A1

公开(公告)日：2008-01-10

申请号：US11818447

申请日：2007-06-13

申请人： Takahiro Shimoirisa ,  Atsumi Kawata ,  Fusaaki Kozawa

发明人： Takahiro Shimoirisa ,  Atsumi Kawata ,  Fusaaki Kozawa

IPC分类号： H02B1/00

CPC分类号： H05K1/14 ,  H05K7/1408 ,  H05K9/0062 ,  H05K2201/044 ,  H05K2201/2018

摘要： The present invention is provided a structure for mounting a printed board in which each connector that is attached to each of a plurality of sub printed boards, which are juxtaposed to one another with respect to a main printed board secured to a metal backboard, is inserted into each of a plurality of connectors that are juxtaposed to one another on the main printed board so that the sub printed boards are mounted on the main printed board by the connector connections. Parts of both ends of an area in proximity to a semiconductor-device mounted area on each of the sub printed boards ate pinched between a first metal frame and a second metal frame so that each of the sub printed boards are secured.

摘要翻译： 本发明提供了一种用于安装印刷电路板的结构，其中插入相对于固定到金属背板的主印刷板彼此并列的多个次印刷电路板中的每一个附接的每个连接器被插入 在主印刷电路板上彼此并置的多个连接器中的每一个连接器中，通过连接器连接将副印刷电路板安装在主印刷电路板上。 在每个副印刷电路板上靠近半导体器件安装区域的区域的两端的部分被夹在第一金属框架和第二金属框架之间，使得每个副印刷电路板被固定。

公开(公告)号：US5281865A

公开(公告)日：1994-01-25

申请号：US797922

申请日：1991-11-26

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Atsumi Kawata ,  Kenji Nagai ,  Kazuhiro Yoshihara ,  Ichiro Imaizumi

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Atsumi Kawata ,  Kenji Nagai ,  Kazuhiro Yoshihara ,  Ichiro Imaizumi

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K19/094 ,  H03K17/16 ,  H03K3/289

CPC分类号： H03K3/356026 ,  H03K19/09429 ,  H03K3/037

摘要： A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.

摘要翻译： 触发器电路接收一对互补数据信号，然后输出与该对互补数据信号对应的互补信号。 一对数据信号也被提供给驱动门装置，该驱动门装置输出与提供给它的一对数据信号的至少一个数据信号对应的信号。 驱动门装置还包括由时钟信号控制的至少一个试用状态门。 驱动门装置的输出信号由存储装置保持，并作为互补输出信号输出。

公开(公告)号：US5021686A

公开(公告)日：1991-06-04

申请号：US470322

申请日：1990-01-25

申请人： Atsumi Kawata ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Kazuhiro Yoshihara ,  Hiroki Yamashita

发明人： Atsumi Kawata ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Kazuhiro Yoshihara ,  Hiroki Yamashita

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0952

CPC分类号： H03K19/00384 ,  H03K19/01707 ,  H03K19/01721 ,  H03K19/0952

摘要： A logic circuit, most suitable for the NOR gate, logic function and integration on a single chip with a plurality of such logic circuits and other digital circuits receiving the outputs of the logic circuits and the logic circuits themselves connected and cascade, wherein plural groups of input transistors are provided, with a load through the voltage source and one of the groups, field effect transistor between the voltage source and the other group, so that its gate is connected to the node between the load and first group and its source is connected to the output terminal, with the improvement being in finding a leakage load for the field effect transistor through the voltage source, providing a clamping circuit for the gate of the transistor. The clamping circuit can include a transistor having its gate connected to the output with a delay so that it will not come on until after a substantial portion of the rise time of the output has expired. An additional logic output may be taken from the gate of this transistor, preferably through a transistor to match the outputs, so that the logic circuit is provided with two independent outputs useful for providing adjacent logic or digital circuits with a conveniently close terminal for input, and further to take advantage of the isolation of the outputs by providing other directions for both outputs for circuit elements that must remain isolated, for example in cross coupling two logic circuits as a flipflop. One or more of the may be a field effect transistor, particularly provided with boot strapping. For otherwise identical logic circuits as a part of an overall integrated logic circuit, the clamping circuits may differ only with respect to matching respective output voltages or respective output currents with respective fan outs or other characteristics of load circuits to be driven by the outputs. Preferably, all of the elements are constructed of field effect transistors.

摘要翻译： 逻辑电路，最适合于NOR门，逻辑功能，并且集成在具有多个这样的逻辑电路的单个芯片上，并且其它数字电路接收逻辑电路和逻辑电路本身连接和级联的输出，其中多组 提供输入晶体管，通过电压源和组中的一个负载，电压源和另一组之间的场效应晶体管，使得其栅极连接到负载和第一组之间的节点，并且其源极被连接 到输出端子，其改进在于通过电压源找到场效应晶体管的泄漏负载，为晶体管的栅极提供钳位电路。 钳位电路可以包括晶体管，其晶体管的栅极连接到输出端延迟，使得在输出的大部分上升时间到期之后，晶体管将不会进入。 可以从该晶体管的栅极获取额外的逻辑输出，优选地通过晶体管来匹配输出，使得逻辑电路具有两个独立的输出，用于向相邻的逻辑或数字电路提供方便的关闭端子用于输入， 并且还通过为必须保持隔离的电路元件的两个输出提供其它方向，例如将两个逻辑电路作为触发器交叉耦合，来利用输出的隔离。 一个或多个可以是场效应晶体管，特别是提供引导带。 对于作为整体集成逻辑电路的一部分的其他相同的逻辑电路，钳位电路可以相对于匹配相应的输出电压或相应的输出电流或相应的输出电流或者相应的输出电流驱动的负载电路的其他特性而不同。 优选地，所有元件由场效应晶体管构成。

公开(公告)号：US5521536A

公开(公告)日：1996-05-28

申请号：US286270

申请日：1994-08-05

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

IPC分类号： H03K19/0175

CPC分类号： H03K19/017545

摘要： In signal transmission lines among logic circuits employed in a semiconductor integrated circuit device, a voltage driver circuit is provided with such a wiring whose length is short, and the function of the signal receiving circuit is achieved by a logic circuit capable of responding to a voltage appearing at a terminal of the wiring. On the other hand, a source terminal of such a wiring whose length is long and whose resistance is high, is voltage-driven by the voltage driver circuit in response to the output voltage of the logic circuit. A current sense circuit is provided with a terminal of this long length wiring, which senses a current flowing through this long length wiring to be converted into a voltage. Both an output resistance of the voltage driver circuit and an input resistance of the current sense circuit are made lower than a DC resistance of this long length wiring.

摘要翻译： 在半导体集成电路装置中使用的逻辑电路之间的信号传输线中，电压驱动电路具有长度短的布线，信号接收电路的功能由能够对电压进行响应的逻辑电路 出现在接线端子处。 另一方面，长度长且电阻较高的布线的源极端子由电压驱动电路根据逻辑电路的输出电压进行电压驱动。 电流检测电路设置有该长度布线的端子，该端子感测流过该长度布线的电流，以转换成电压。 电压驱动电路的输出电阻和电流检测电路的输入电阻均低于该长度布线的直流电阻。

公开(公告)号：US5426784A

公开(公告)日：1995-06-20

申请号：US16532

申请日：1993-02-11

申请人： Atsumi Kawata ,  Hirotoshi Tanaka ,  Hiroki Yamashita ,  Kenji Nagai ,  Minoru Yamada ,  Nobuhiro Taniguchi

发明人： Atsumi Kawata ,  Hirotoshi Tanaka ,  Hiroki Yamashita ,  Kenji Nagai ,  Minoru Yamada ,  Nobuhiro Taniguchi

IPC分类号： G06F5/00 ,  H03M9/00 ,  G06F1/04

CPC分类号： H03M9/00

摘要： A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108. Thus only the shift register 10, performs high-speed operations at the same timing as the received serial data, and the other circuits operate at slower speeds whose timing is several times longer than that of the serial data received, thereby eliminating complex timing and averting difficulty control logic.

摘要翻译： 移位寄存器10接收串行数据并且与所接收的串行数据的定时同步地输出并行数据。 移位寄存器组20,21从移位寄存器10接收并行数据的位输出。移位寄存器组中的移位寄存器20,21的位数被设定在对应于并行的位输出的一定条件 提供了多个符合电路107,108，其检测预设数据起始模式与移位寄存器组中的数据的位排列之间的一致性。 选择器306根据来自符合电路107,108的输出信号从移位寄存器组中选择一组并行输出。因此，只有移位寄存器10在与所接收的串行数据相同的定时进行高速操作，以及 其他电路以较慢的速度工作，其定时比接收的串行数据的时间长几倍，从而消除复杂的时序并避免难度控制逻辑。