公开(公告)号：US5021686A

公开(公告)日：1991-06-04

申请号：US470322

申请日：1990-01-25

申请人： Atsumi Kawata ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Kazuhiro Yoshihara ,  Hiroki Yamashita

发明人： Atsumi Kawata ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Kazuhiro Yoshihara ,  Hiroki Yamashita

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0952

CPC分类号： H03K19/00384 ,  H03K19/01707 ,  H03K19/01721 ,  H03K19/0952

摘要： A logic circuit, most suitable for the NOR gate, logic function and integration on a single chip with a plurality of such logic circuits and other digital circuits receiving the outputs of the logic circuits and the logic circuits themselves connected and cascade, wherein plural groups of input transistors are provided, with a load through the voltage source and one of the groups, field effect transistor between the voltage source and the other group, so that its gate is connected to the node between the load and first group and its source is connected to the output terminal, with the improvement being in finding a leakage load for the field effect transistor through the voltage source, providing a clamping circuit for the gate of the transistor. The clamping circuit can include a transistor having its gate connected to the output with a delay so that it will not come on until after a substantial portion of the rise time of the output has expired. An additional logic output may be taken from the gate of this transistor, preferably through a transistor to match the outputs, so that the logic circuit is provided with two independent outputs useful for providing adjacent logic or digital circuits with a conveniently close terminal for input, and further to take advantage of the isolation of the outputs by providing other directions for both outputs for circuit elements that must remain isolated, for example in cross coupling two logic circuits as a flipflop. One or more of the may be a field effect transistor, particularly provided with boot strapping. For otherwise identical logic circuits as a part of an overall integrated logic circuit, the clamping circuits may differ only with respect to matching respective output voltages or respective output currents with respective fan outs or other characteristics of load circuits to be driven by the outputs. Preferably, all of the elements are constructed of field effect transistors.

摘要翻译： 逻辑电路，最适合于NOR门，逻辑功能，并且集成在具有多个这样的逻辑电路的单个芯片上，并且其它数字电路接收逻辑电路和逻辑电路本身连接和级联的输出，其中多组 提供输入晶体管，通过电压源和组中的一个负载，电压源和另一组之间的场效应晶体管，使得其栅极连接到负载和第一组之间的节点，并且其源极被连接 到输出端子，其改进在于通过电压源找到场效应晶体管的泄漏负载，为晶体管的栅极提供钳位电路。 钳位电路可以包括晶体管，其晶体管的栅极连接到输出端延迟，使得在输出的大部分上升时间到期之后，晶体管将不会进入。 可以从该晶体管的栅极获取额外的逻辑输出，优选地通过晶体管来匹配输出，使得逻辑电路具有两个独立的输出，用于向相邻的逻辑或数字电路提供方便的关闭端子用于输入， 并且还通过为必须保持隔离的电路元件的两个输出提供其它方向，例如将两个逻辑电路作为触发器交叉耦合，来利用输出的隔离。 一个或多个可以是场效应晶体管，特别是提供引导带。 对于作为整体集成逻辑电路的一部分的其他相同的逻辑电路，钳位电路可以相对于匹配相应的输出电压或相应的输出电流或相应的输出电流或者相应的输出电流驱动的负载电路的其他特性而不同。 优选地，所有元件由场效应晶体管构成。

公开(公告)号：US5281865A

公开(公告)日：1994-01-25

申请号：US797922

申请日：1991-11-26

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Atsumi Kawata ,  Kenji Nagai ,  Kazuhiro Yoshihara ,  Ichiro Imaizumi

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Atsumi Kawata ,  Kenji Nagai ,  Kazuhiro Yoshihara ,  Ichiro Imaizumi

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K19/094 ,  H03K17/16 ,  H03K3/289

CPC分类号： H03K3/356026 ,  H03K19/09429 ,  H03K3/037

摘要： A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.

摘要翻译： 触发器电路接收一对互补数据信号，然后输出与该对互补数据信号对应的互补信号。 一对数据信号也被提供给驱动门装置，该驱动门装置输出与提供给它的一对数据信号的至少一个数据信号对应的信号。 驱动门装置还包括由时钟信号控制的至少一个试用状态门。 驱动门装置的输出信号由存储装置保持，并作为互补输出信号输出。

公开(公告)号：US5426784A

公开(公告)日：1995-06-20

申请号：US16532

申请日：1993-02-11

申请人： Atsumi Kawata ,  Hirotoshi Tanaka ,  Hiroki Yamashita ,  Kenji Nagai ,  Minoru Yamada ,  Nobuhiro Taniguchi

发明人： Atsumi Kawata ,  Hirotoshi Tanaka ,  Hiroki Yamashita ,  Kenji Nagai ,  Minoru Yamada ,  Nobuhiro Taniguchi

IPC分类号： G06F5/00 ,  H03M9/00 ,  G06F1/04

CPC分类号： H03M9/00

摘要： A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108. Thus only the shift register 10, performs high-speed operations at the same timing as the received serial data, and the other circuits operate at slower speeds whose timing is several times longer than that of the serial data received, thereby eliminating complex timing and averting difficulty control logic.

摘要翻译： 移位寄存器10接收串行数据并且与所接收的串行数据的定时同步地输出并行数据。 移位寄存器组20,21从移位寄存器10接收并行数据的位输出。移位寄存器组中的移位寄存器20,21的位数被设定在对应于并行的位输出的一定条件 提供了多个符合电路107,108，其检测预设数据起始模式与移位寄存器组中的数据的位排列之间的一致性。 选择器306根据来自符合电路107,108的输出信号从移位寄存器组中选择一组并行输出。因此，只有移位寄存器10在与所接收的串行数据相同的定时进行高速操作，以及 其他电路以较慢的速度工作，其定时比接收的串行数据的时间长几倍，从而消除复杂的时序并避免难度控制逻辑。

公开(公告)号：US5521536A

公开(公告)日：1996-05-28

申请号：US286270

申请日：1994-08-05

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

IPC分类号： H03K19/0175

CPC分类号： H03K19/017545

摘要： In signal transmission lines among logic circuits employed in a semiconductor integrated circuit device, a voltage driver circuit is provided with such a wiring whose length is short, and the function of the signal receiving circuit is achieved by a logic circuit capable of responding to a voltage appearing at a terminal of the wiring. On the other hand, a source terminal of such a wiring whose length is long and whose resistance is high, is voltage-driven by the voltage driver circuit in response to the output voltage of the logic circuit. A current sense circuit is provided with a terminal of this long length wiring, which senses a current flowing through this long length wiring to be converted into a voltage. Both an output resistance of the voltage driver circuit and an input resistance of the current sense circuit are made lower than a DC resistance of this long length wiring.

摘要翻译： 在半导体集成电路装置中使用的逻辑电路之间的信号传输线中，电压驱动电路具有长度短的布线，信号接收电路的功能由能够对电压进行响应的逻辑电路 出现在接线端子处。 另一方面，长度长且电阻较高的布线的源极端子由电压驱动电路根据逻辑电路的输出电压进行电压驱动。 电流检测电路设置有该长度布线的端子，该端子感测流过该长度布线的电流，以转换成电压。 电压驱动电路的输出电阻和电流检测电路的输入电阻均低于该长度布线的直流电阻。

公开(公告)号：US4954866A

公开(公告)日：1990-09-04

申请号：US247250

申请日：1988-09-21

申请人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

发明人： Hirotoshi Tanaka ,  Hiroki Yamashita ,  Noboru Masuda ,  Junji Shigeta ,  Yasunari Umemoto ,  Osamu Kagaya

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/0605 ,  H01L27/1116 ,  H01L27/105

摘要： A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.

摘要翻译： 公开了一种半导体集成电路存储器，其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层，例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层 第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式，并且被划分为至少第一和第二区域。 例如，形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成，并且第二区域形成在外围电路部分的电路元件之下 由载流子浓度低的P型层构成。 形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫，即使当存储单元的尺寸精细时。 此外，形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力，并且可以抑制在外部电路部分的寄生电容的增加 外围电路部分保持高速运行的内存。

公开(公告)号：US4586169A

公开(公告)日：1986-04-29

申请号：US440723

申请日：1982-11-10

申请人： Hiroyuki Itoh ,  Akira Masaki ,  Hiroki Yamashita ,  Satoshi Hososaka

发明人： Hiroyuki Itoh ,  Akira Masaki ,  Hiroki Yamashita ,  Satoshi Hososaka

IPC分类号： H01L21/822 ,  G11C11/411 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L27/04 ,  H01L27/10 ,  H01L27/118 ,  H03K3/2885 ,  H03K19/173 ,  G11C7/00 ,  G11C11/40 ,  G11C15/00

CPC分类号： G11C11/4113 ,  H03K19/1735 ,  H03K3/2885

摘要： A large scale integrated circuit including therein a logical gate circuit and a memory circuit is disclosed in which a large number of circuit blocks each having the same structure and including at least eight transistors and at least five resistors are arranged on a chip, and the logical gate circuit or memory circuit has a selected wiring pattern of the transistors and resistors included in the circuit block.

摘要翻译： 公开了一种包括逻辑门电路和存储电路的大规模集成电路，其中每个具有相同结构并且包括至少八个晶体管和至少五个电阻器的大量电路块布置在芯片上，逻辑 门电路或存储器电路具有包括在电路块中的晶体管和电阻器的选定布线图案。

公开(公告)号：US5396198A

公开(公告)日：1995-03-07

申请号：US118178

申请日：1993-09-09

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Keiichirou Nakanishi ,  Tatsuya Saitoh ,  Tohru Kobayashi ,  Satoru Isomura

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Keiichirou Nakanishi ,  Tatsuya Saitoh ,  Tohru Kobayashi ,  Satoru Isomura

IPC分类号： H01L23/528 ,  H01L23/66 ,  H01P5/12 ,  H01P1/26

CPC分类号： H01L23/5286 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011

摘要： A power source wiring supplies power to individual electronic circuits constituting an electronic circuit device. Load circuits are connected to the power source wiring within the range of an arrival time of a voltage noise occurring in the power source wiring in a time of about a half of a pulse width of a noise current at the time of the operation of the electronic circuit. Each of these load circuits includes a series circuit of a resistance and a capacitance.

摘要翻译： 电源线为构成电子电路装置的各电子线路供电。 负载电路在电子线路中发生的电压噪声的到达时间的范围内连接到电源布线，时间为电子操作时的噪声电流的脉冲宽度的大约一半 电路。 这些负载电路中的每一个都包括电阻和电容的串联电路。

公开(公告)号：US08993952B2

公开(公告)日：2015-03-31

申请号：US13546382

申请日：2012-07-11

申请人： Takashi Takemoto ,  Hiroki Yamashita ,  Shinji Tsuji

发明人： Takashi Takemoto ,  Hiroki Yamashita ,  Shinji Tsuji

IPC分类号： H01J40/14 ,  H03F3/08 ,  H03F1/02 ,  H03F1/08

CPC分类号： H03F3/085 ,  H03F1/0222 ,  H03F1/0233 ,  H03F1/083 ,  H03F3/087 ,  H03F2200/372 ,  H03F2200/504 ,  H03F2200/78

摘要： An optical module including a transimpedance amplifier capable of realizing a high-speed and high-quality receiving operation is provided. A transimpedance amplifier includes: a pre-amplifier using a single-end current signal as an input and converting the single-end current signal to a single-end voltage signal; an automatic decision threshold control detecting a center electric potential of the single-end voltage signal serving as an output of the pre-amplifier; a post-amplifier differentiating and amplifying the single-end voltage signal of the output of the pre-amplifier; and a power circuit supplying power to the pre-amplifier. Particularly, in accordance with an input voltage signal or an output voltage signal of the pre-amplifier, the power circuit outputs a varied current that flows to a supply terminal of the pre-amplifier and a varied current having a phase opposite to that of the varied current. Thus, the power supply current change is cancelled out.

摘要翻译： 提供一种包括能够实现高速和高质量接收操作的跨阻放大器的光学模块。 跨阻放大器包括：使用单端电流信号作为输入并将单端电流信号转换为单端电压信号的前置放大器; 检测用作前置放大器的输出的单端电压信号的中心电位的自动判定阈值控制; 后置放大器对前置放大器输出的单端电压信号进行差分放大; 以及向前置放大器供电的电源电路。 特别地，根据前置放大器的输入电压信号或输出电压信号，电源电路输出流向前置放大器的电源端子的变化的电流和与 变化的电流。 因此，电源电流变化被消除。

公开(公告)号：US08871602B2

公开(公告)日：2014-10-28

申请号：US13422488

申请日：2012-03-16

申请人： Hiroki Yamashita

发明人： Hiroki Yamashita

IPC分类号： H01L21/02 ,  H01L27/28 ,  G11C13/00 ,  H01L51/05

CPC分类号： G11C13/0016 ,  G11C13/0014 ,  H01L27/285 ,  H01L51/0003 ,  H01L51/0021 ,  H01L51/0591 ,  H01L51/0595

摘要： According to one embodiment, a method for manufacturing a molecular memory device includes: forming a first wiring layer including a plurality of first wirings extending in a first direction; forming a sacrificial film on the first wiring layer; forming a plurality of core members on the first wiring layer, the core member extending in a second direction crossing the first direction and being formed from an insulating material different from the sacrificial film; forming a second wiring on a side surface of the core member; removing a portion of the sacrificial film located immediately below the second wiring; embedding a polymer; and embedding an insulating. The embedding a polymer includes embedding a polymer serving as a memory material between the first wiring and the second wiring. The embedding an insulating member includes embedding an insulating member in a space between the second wirings between the core members.

摘要翻译： 根据一个实施例，一种用于制造分子存储器件的方法包括：形成包括沿第一方向延伸的多个第一布线的第一布线层; 在第一布线层上形成牺牲膜; 在所述第一布线层上形成多个芯构件，所述芯构件沿与所述第一方向交叉的第二方向延伸并且由与所述牺牲膜不同的绝缘材料形成; 在所述芯构件的侧表面上形成第二布线; 去除位于第二布线正下方的牺牲膜的一部分; 嵌入聚合物; 并嵌入绝缘。 嵌入聚合物包括在第一布线和第二布线之间嵌入用作存储材料的聚合物。 嵌入绝缘构件包括将绝缘构件嵌入在芯构件之间的第二布线之间的空间中。

公开(公告)号：US08503595B2

公开(公告)日：2013-08-06

申请号：US13255902

申请日：2009-09-29

申请人： Koji Fukuda ,  Hiroki Yamashita

发明人： Koji Fukuda ,  Hiroki Yamashita

IPC分类号： H03K5/26

CPC分类号： H03K5/26 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/033

摘要： The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C_GOOD and C_BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C_GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted. Depending on a relation among data outputs of total three symbols obtained by combining a symbol and symbols previous and subsequent thereto, it is selected that either the Early or the Late is to be outputted by a decision logic EL_LOGIC.

摘要翻译： 本发明涉及一种包括时钟产生电路的时钟发生电路和信号再现电路，更具体地说，本发明提供一种能够通过单相时钟执行数据判断和相位比较两者的数据判断/相位比较电路 并且提供包括数据判断/相位比较电路的CDR（时钟数据恢复）电路。 相同的数据和时钟输入到具有正确判断数据所需的不同数据确定周期（建立/保持时间）的两个数据判断单元C_GOOD和C_BAD，并且具有较短的所需数据确定的数据判断单元C_GOOD的输出 将周期作为数据判断/相位比较电路的数据输出。 当两个数据判断单元的输出彼此不同时，输出表示时钟相位太早的信号Early，或指示时钟相位太迟的信号Late。 根据通过组合符号和先前和之后的符号获得的总共三个符号的数据输出之间的关系，选择Early或Late由判决逻辑EL_LOGIC输出。