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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20120249180A1

    公开(公告)日：2012-10-04

    申请号：US13429056

    申请日：2012-03-23

    申请人： Takamasa SUZUKI ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

    发明人： Takamasa SUZUKI ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

    IPC分类号： H03K19/0175

    CPC分类号： H03K3/35613

    摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.

    摘要翻译： 本文公开了一种可用于电平移位电路的装置。 该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路， 第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管 电源线，使第五晶体管不导通以使第一反相器停用;以及控制电路，被配置为在第一反相器停用期间防止输出端子进入电浮动状态。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08638121B2

    公开(公告)日：2014-01-28

    申请号：US13429056

    申请日：2012-03-23

    申请人： Takamasa Suzuki ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

    发明人： Takamasa Suzuki ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura

    IPC分类号： H03K19/0175

    CPC分类号： H03K3/35613

    摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.

    摘要翻译： 本文公开了一种可用于电平移位电路的装置。 该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路， 第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管 所述第一晶体管被导通以使所述第一反相器无效;以及控制电路，被配置为在所述第一反相器的停用期间防止所述输出端子进入电浮动状态。

    SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF 审中-公开
    具有开放式线型存储器单元阵列的半导体存储器件及其控制方法

    公开(公告)号：US20110176379A1

    公开(公告)日：2011-07-21

    申请号：US13008408

    申请日：2011-01-18

    申请人： Shinichi TAKAYAMA ,  Akira Kotabe ,  Kazuo Ono ,  Tomonori Sekiguchi ,  Yoshimitsu Yanagawa ,  Riichiro Takemura

    发明人： Shinichi TAKAYAMA ,  Akira Kotabe ,  Kazuo Ono ,  Tomonori Sekiguchi ,  Yoshimitsu Yanagawa ,  Riichiro Takemura

    IPC分类号： G11C7/06

    CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

    摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.

    摘要翻译： 半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。 写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位 在第二位线的数据写入时的第二本地数据线。

    Timing control circuit, timing generation system, timing control method and semiconductor memory device
    4.
    发明授权
    Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
    定时控制电路，定时生成系统，定时控制方法和半导体存储器件

    公开(公告)号：US07750712B2

    公开(公告)日：2010-07-06

    申请号：US12314207

    申请日：2008-12-05

    申请人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

    发明人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

    IPC分类号： H03H11/26

    CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C19/00 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03K2005/00241

    摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.

    摘要翻译： 定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟 延迟元件 定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。 粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。 精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。 定时信号延迟的变化减小。

    Timing control circuit, timing generation system, timing control method and semiconductor memory device
    5.
    发明申请
    Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
    定时控制电路，定时生成系统，定时控制方法和半导体存储器件

    公开(公告)号：US20090146716A1

    公开(公告)日：2009-06-11

    申请号：US12314207

    申请日：2008-12-05

    申请人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

    发明人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

    IPC分类号： H03H11/26

    CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C19/00 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03K2005/00241

    摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.

    摘要翻译： 定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟 延迟元件 定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。 粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。 精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。 定时信号延迟的变化减小。

    SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET 有权
    具有放大偏差的感测放大器电路的半导体存储器件

    公开(公告)号：US20110079858A1

    公开(公告)日：2011-04-07

    申请号：US12967728

    申请日：2010-12-14

    申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

    发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

    IPC分类号： H01L27/108

    CPC分类号： G11C11/4091 ,  H01L27/10897

    摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

    摘要翻译： 具有高集成度，低功耗和高操作速度的半导体存储器件。 存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。 构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。 具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。 数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。

    Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages
    8.
    发明授权
    Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages 有权
    半导体存储器件包括具有P型读出放大器和具有不同阈值电压的N型读出放大器的读出放大器

    公开(公告)号：US07843751B2

    公开(公告)日：2010-11-30

    申请号：US12352347

    申请日：2009-01-12

    申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

    发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

    IPC分类号： G11C7/02

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

    摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

    摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07633833B2

    公开(公告)日：2009-12-15

    申请号：US12028788

    申请日：2008-02-09

    申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

    发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

    IPC分类号： G11C8/00

    CPC分类号： G11C7/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

    摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

    摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

    Semiconductor device
    10.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20090086551A1

    公开(公告)日：2009-04-02

    申请号：US12285204

    申请日：2008-09-30

    申请人： Akira Ide ,  Yasuhiro Takai ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Akira Ide ,  Yasuhiro Takai ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C7/00 ,  G06F11/00 ,  G06F11/10 ,  G11C8/00

    CPC分类号： G11C11/4093 ,  G06F11/1004 ,  G11C7/1006 ,  G11C7/1012 ,  G11C8/12

    摘要： Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin.

    摘要翻译： 公开了一种半导体器件，其中如果以第一字配置从第一输出引脚输出的数据组以第二字配置从第一输出引脚和第二输出引脚输出，并且从第三输出输出数据组 第一字配置中的引脚以第二字配置从第三输出引脚和第四输出引脚输出，第二输出引脚被布置为与第一输出引脚相邻，并且第四输出引脚被布置为与第三输出引脚 。