公开(公告)号：US5017998A

公开(公告)日：1991-05-21

申请号：US572597

申请日：1990-08-27

申请人： Takao Miura ,  Kazunori Imaoka ,  Fumitoshi Sugimoto

发明人： Takao Miura ,  Kazunori Imaoka ,  Fumitoshi Sugimoto

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76264 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76286

摘要： In a direct bonded SOI substrate where the SiO.sub.2 films OA, OB are respectively provided on the single surfaces of the silicon substrates A, B, at least any one of SiO.sub.2 films OA, OB has thickness of 1 .mu.m or more. These SiO.sub.2 films OA, OB are bonded and moreover the one silicon substrate B of such a bonded substrate is ground to thickness of about 1 .mu.m. A semiconductor device having a trench structure wherein the trench formed on the silicon substrate B passes through the interface between the SiO.sub.2 film OB and the SiO.sub.2 film OA. The bottom of such a trench is located within the SiO.sub.2 film OA and the bottom of the polycrystalline silicon conductive film within the trench is located within the SiO.sub.2 film OA rather than the interface between the silicon substrate B and SiO.sub.2 film OB.

摘要翻译： 在SiO 2膜OA，OB分别设置在硅衬底A，B的单个表面上的直接键合SOI衬底中，SiO 2膜OA，OB中的至少任一个具有1μm或更大的厚度。 这些SiO 2膜OA，OB接合，此外，将这种键合衬底的一个硅衬底B研磨成约1μm的厚度。 具有沟槽结构的半导体器件，其中形成在硅衬底B上的沟槽穿过SiO 2膜OB和SiO 2膜OA之间的界面。 这种沟槽的底部位于SiO 2膜OA内，并且沟槽内的多晶硅导电膜的底部位于SiO 2膜OA内，而不是硅衬底B和SiO 2膜OB之间的界面。

公开(公告)号：US20080020329A1

公开(公告)日：2008-01-24

申请号：US11593527

申请日：2006-11-07

申请人： Fumitoshi Sugimoto

发明人： Fumitoshi Sugimoto

IPC分类号： G03F7/20

CPC分类号： G03F7/70441 ,  G03F7/70466

摘要： The method for fabricating the semiconductor device includes the step of forming a photoresist film 84 over a substrate 10, the step of exposing interconnection patterns to the photoresist film 84, the step of exposing to the photoresist film 84 hole patterns of a plurality of holes positioned at ends or bent portions of the interconnection patterns where holes to be connected to the interconnection patterns are to be formed, and the step of developing the photoresist film 84 with the interconnection patterns and the holes patterns exposed to. Thus, the insufficient exposure energy at the ends or the bent portions of the patterns due to optical proximity effect is compensated to prevent the shortening at the pattern ends or the rounding at the pattern bent portions. The contacts with the contact plugs connected to the pattern ends or the pattern bent portions can be ensured.

摘要翻译： 制造半导体器件的方法包括在衬底10上形成光致抗蚀剂膜84的步骤，将互连图案暴露于光致抗蚀剂膜84的步骤，暴露于光致抗蚀剂膜84的步骤，定位多个孔的孔图案 在要连接到互连图形的孔的互连图案的端部或弯曲部分处，以及暴露于互连图案和孔图案的光致抗蚀剂膜84的显影步骤。 因此，补偿了由于光学邻近效应导致的图案的端部或弯曲部分处的不足的曝光能量，以防止图案端部的缩短或图案弯曲部分的圆整。 可以确保与连接到图案端部的接触插塞或图案弯曲部分的触点。

公开(公告)号：US20070166627A1

公开(公告)日：2007-07-19

申请号：US11411019

申请日：2006-04-26

申请人： Fumitoshi Sugimoto

发明人： Fumitoshi Sugimoto

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F7/70466 ,  G03F1/70

摘要： In order to form a transfer pattern of desired size with high accuracy, a method for manufacturing a semiconductor device includes a process of forming the transfer pattern including a line whose width and angle varies, by performing multiple exposure using a plurality of masks having different patterns over different mask substrates.

摘要翻译： 为了高精度地形成期望尺寸的转印图案，制造半导体器件的方法包括通过使用具有不同图案的多个掩模进行多次曝光来形成包括其宽度和角度变化的线的转印图案的处理 在不同的掩模基板上。

公开(公告)号：US07887977B2

公开(公告)日：2011-02-15

申请号：US12068694

申请日：2008-02-11

申请人： Fumitoshi Sugimoto

发明人： Fumitoshi Sugimoto

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： A mask formed with a mask pattern is prepared, the mask pattern having a shape that a base pattern is divided into at least two partial patterns disposed at a space narrower than a resolution limit. A first relation is acquired between a width of the space separating the partial patterns and a size of a pattern on a substrate formed by transferring the mask pattern. The width of the space separating the partial patterns is determined in accordance with the size of a pattern to be formed on the substrate and the first relation. A mask pattern is formed having at least two separated partial patterns on a mask in accordance with the determined width of the space.

摘要翻译： 制备了具有掩模图案的掩模，掩模图案具有将基部图案划分为以比分辨率极限窄的空间设置的至少两个部分图案的形状。 在分离部分图案的空间的宽度和通过转印掩模图案形成的基板上的图案的尺寸之间获取第一关系。 分离部分图案的空间的宽度根据要在基板上形成的图案的大小和第一关系来确定。 根据确定的空间宽度，在掩模上形成具有至少两个分开的部分图案的掩模图案。

公开(公告)号：US5562529A

公开(公告)日：1996-10-08

申请号：US131949

申请日：1993-10-08

申请人： Sadahiro Kishii ,  Yoshihiro Arimoto ,  Hiroshi Horie ,  Fumitoshi Sugimoto

发明人： Sadahiro Kishii ,  Yoshihiro Arimoto ,  Hiroshi Horie ,  Fumitoshi Sugimoto

IPC分类号： B24B37/013 ,  B24B49/10 ,  B24B1/00 ,  B24B7/16

CPC分类号： B24B37/013 ,  B24B49/10 ,  Y10S451/908

摘要： An apparatus and method for polishing a semiconductor wafer. A polisher includes a supporting plate having a conductive film and a polishing cloth formed on the conductive film of the supporting plate. The polishing cloth has a plurality of openings to expose the conductive film. A wafer holder has a conductive wafer holding surface to hold a semiconductor wafer having current detective patterns and an insulating film covering the current detective patterns. A polishing slurry supply device supplies a polishing slurry including ions to either the polishing cloth or the semiconductor wafer. A current detecting device, connected to the supporting plate and the wafer holder, detects a magnitude of a current flowing across the supporting plate and the wafer holder through the conductive wafer holding surface, the semiconductor wafer held by the wafer holder, the current detective patterns of the semiconductor wafer, the polishing slurry filled in the openings of the polishing cloth, and the conductive film.

摘要翻译： 一种用于抛光半导体晶片的装置和方法。 抛光机包括具有导电膜的支撑板和形成在支撑板的导电膜上的抛光布。 抛光布具有多个开口以露出导电膜。 晶片保持器具有导电晶片保持表面，以保持具有电流检测图案的半导体晶片和覆盖当前检测图案的绝缘膜。 研磨浆料供给装置将包含离子的研磨浆料供给到研磨布或半导体晶片。 连接到支撑板和晶片保持器的电流检测装置检测通过导电晶片保持表面流过支撑板和晶片保持器的电流的大小，由晶片保持器保持的半导体晶片，当前的检测模式 的半导体晶片，填充在抛光布的开口中的抛光浆料和导电膜。

公开(公告)号：US07741016B2

公开(公告)日：2010-06-22

申请号：US11593527

申请日：2006-11-07

申请人： Fumitoshi Sugimoto

发明人： Fumitoshi Sugimoto

IPC分类号： G03F7/00

CPC分类号： G03F7/70441 ,  G03F7/70466

摘要： The method for fabricating the semiconductor device includes the step of forming a photoresist film 84 over a substrate 10, the step of exposing interconnection patterns to the photoresist film 84, the step of exposing to the photoresist film 84 hole patterns of a plurality of holes positioned at ends or bent portions of the interconnection patterns where holes to be connected to the interconnection patterns are to be formed, and the step of developing the photoresist film 84 with the interconnection patterns and the holes patterns exposed to. Thus, the insufficient exposure energy at the ends or the bent portions of the patterns due to optical proximity effect is compensated to prevent the shortening at the pattern ends or the rounding at the pattern bent portions. The contacts with the contact plugs connected to the pattern ends or the pattern bent portions can be ensured.

摘要翻译： 制造半导体器件的方法包括在衬底10上形成光致抗蚀剂膜84的步骤，将互连图案暴露于光致抗蚀剂膜84的步骤，暴露于光致抗蚀剂膜84的步骤，定位多个孔的孔图案 在要连接到互连图形的孔的互连图案的端部或弯曲部分处，以及暴露于互连图案和孔图案的光致抗蚀剂膜84的显影步骤。 因此，补偿了由于光学邻近效应导致的图案的端部或弯曲部分处的不足的曝光能量，以防止图案端部的缩短或图案弯曲部分的圆整。 可以确保与连接到图案端部的接触插塞或图案弯曲部分的触点。

公开(公告)号：US20060003235A1

公开(公告)日：2006-01-05

申请号：US10991461

申请日：2004-11-19

申请人： Fumitoshi Sugimoto

发明人： Fumitoshi Sugimoto

IPC分类号： G03F7/00

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/70433 ,  H01L21/0274

摘要： A semiconductor manufacturing method is disclosed. The method includes a lithography process having an exposure step for projecting an image of a mask pattern of a mask onto a photo resist layer using exposure light. The mask pattern includes a first pattern having a light transparency characteristic corresponding to a circuit pattern, and a second pattern having an inverted light transparency characteristic arranged within and spaced apart from the first pattern.

摘要翻译： 公开了一种半导体制造方法。 该方法包括具有曝光步骤的光刻工艺，用于使用曝光光将掩模的掩模图案的图像投影到光致抗蚀剂层上。 掩模图案包括具有对应于电路图案的透光特性的第一图案和布置在第一图案内并与第一图案间隔开的具有倒置的透光特性的第二图案。

公开(公告)号：US5506433A

公开(公告)日：1996-04-09

申请号：US277022

申请日：1994-08-24

申请人： Tatsuya Ohori ,  Isamu Hanyu ,  Fumitoshi Sugimoto ,  Yoshihiro Arimoto

发明人： Tatsuya Ohori ,  Isamu Hanyu ,  Fumitoshi Sugimoto ,  Yoshihiro Arimoto

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L27/01 ,  H01L29/04

CPC分类号： H01L21/76256 ,  H01L21/2007 ,  Y10S148/135

摘要： A silicon-on-insulator (SOI) structure having a single crystal layer of a group III-V compound semiconductor material contacting a single crystal substrate of sapphire such that a principal surface of the single crystal layer establishes an intimate contact with a corresponding principal surface of the single crystal substrate and the single crystal layer, and the single crystal substrate are bonded with each other while elevating a temperature.

摘要翻译： 一种绝缘体上硅（SOI）结构，其具有接触蓝宝石单晶衬底的III-V族化合物半导体材料的单晶层，使得单晶层的主表面与相应的主表面紧密接触 的单晶衬底和单晶层，并且单晶衬底在升高温度的同时彼此接合。

公开(公告)号：US07820364B2

公开(公告)日：2010-10-26

申请号：US11411019

申请日：2006-04-26

申请人： Fumitoshi Sugimoto

发明人： Fumitoshi Sugimoto

IPC分类号： G03F7/00 ,  G03F1/00 ,  G03C5/00

CPC分类号： G03F7/70466 ,  G03F1/70

摘要： In order to form a transfer pattern of desired size with high accuracy, a method for manufacturing a semiconductor device includes a process of forming the transfer pattern including a line whose width and angle varies, by performing multiple exposure using a plurality of masks having different patterns over different mask substrates.

摘要翻译： 为了高精度地形成期望尺寸的转印图案，制造半导体器件的方法包括通过使用具有不同图案的多个掩模进行多次曝光来形成包括其宽度和角度变化的线的转印图案的处理 在不同的掩模基板上。

公开(公告)号：US07678693B2

公开(公告)日：2010-03-16

申请号：US11595917

申请日：2006-11-13

申请人： Fumitoshi Sugimoto ,  Kiyoshi Ozawa

发明人： Fumitoshi Sugimoto ,  Kiyoshi Ozawa

IPC分类号： H01L21/4763

CPC分类号： G03F7/70466 ,  G03F1/36 ,  G03F1/50 ,  G03F1/70 ,  G03F7/70433 ,  H01L21/76808 ,  H01L21/76816 ,  Y10S438/945

摘要： An exposure method executed after processing a hole in a substrate of a semiconductor device, has an exposure step of transferring a pattern on a mask onto an upper layer of the hole and forming a wiring groove by exposure, wherein a quantity of exposure with which a wiring groove 11 just above the hole or the wiring groove in the vicinity of the hole is exposed to light, is greater than a quantity of exposure with which a wiring groove 11A in a position spaced away from just above the hole is exposed to the light.

摘要翻译： 在半导体器件的基板中处理孔之后执行的曝光方法具有将掩模上的图案转印到孔的上层上并通过曝光形成布线槽的曝光步骤，其中曝光量 在孔附近的布线槽11或孔附近的布线槽暴露于光，大于在与孔正上方隔开的位置上的布线槽11A暴露于光的曝光量 。