公开(公告)号：US4843289A

公开(公告)日：1989-06-27

申请号：US161316

申请日：1988-02-23

申请人： Takao Mogi ,  Keiji Yuzawa ,  Yoshinori Komiya ,  Masayuki Suematsu ,  Fujio Tagami

发明人： Takao Mogi ,  Keiji Yuzawa ,  Yoshinori Komiya ,  Masayuki Suematsu ,  Fujio Tagami

IPC分类号： H04B1/20 ,  H04N5/44

CPC分类号： H04N5/44 ,  H04B1/205

摘要： Digitally controllable ICs or function blocks in an electronic apparatus are connected through control bus lines, and a switch device is provided for disconnecting one of the digitally controllable ICs or function blocks from the control bus so that the control bus is not disabled when that one IC is turned off or is not occupied when the IC is operating in its internal processing mode. Therefore, communication between the remaining ICs can be maintained through the control bus.

摘要翻译： 电子设备中的数字可控IC或功能块通过控制总线连接，并且提供开关装置用于将数字可控IC或功能块中的一个与控制总线断开，使得当该一个IC 当IC处于其内部处理模式时，它被关闭或不被占用。 因此，可以通过控制总线来保持剩余IC之间的通信。

公开(公告)号：US4743968A

公开(公告)日：1988-05-10

申请号：US831876

申请日：1986-02-24

申请人： Takao Mogi ,  Masayuki Suematsu ,  Kosuke Fujita

发明人： Takao Mogi ,  Masayuki Suematsu ,  Kosuke Fujita

IPC分类号： H04L12/40 ,  H04N7/00 ,  H04N5/44

CPC分类号： H04N5/44

摘要： A system for controlling electronic apparatus, such as a television receiver, which employs a control circuit having a control program in a read only memory to sequentially communicate over an internal system bus in a predetermined interval with a plurality of controllable, operational circuit blocks forming the electronic apparatus, in which the control circuit selects a specific circuit block for data transfer upon a request signal. In one embodiment, a request signal is transmitted prior to a vertical blanking interval in a television signal and in another embodiment, a dedicated line is provided from a selected controllable unit to the control unit, whereby the request signal can be transmitted at any time, irrespective of whether data is being transferred at such time.

摘要翻译： 一种用于控制诸如电视接收机的电子设备的系统，其采用具有在只读存储器中的控制程序的控制电路，以在预定间隔内通过内部系统总线顺序地与多个可控的操作电路块形成 电子设备，其中控制电路根据请求信号选择用于数据传输的特定电路块。 在一个实施例中，在电视信号中的垂直消隐间隔之前发送请求信号，在另一个实施例中，从所选择的可控单元向控制单元提供专用线路，从而可以随时发送请求信号， 无论数据是否在此时传输。

公开(公告)号：US4805085A

公开(公告)日：1989-02-14

申请号：US203616

申请日：1988-06-06

申请人： Takao Mogi ,  Masayuki Suematsu

发明人： Takao Mogi ,  Masayuki Suematsu

IPC分类号： G05B15/02 ,  G05B19/042 ,  G06F13/20 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177 ,  G06F15/46 ,  G06F11/16

CPC分类号： G05B19/0421

摘要： A digital control system for electronic apparatus employs an internal bus system and includes at least one master controller and a plurality of operational circuits connected via control bus lines so that, during normal operation of the electronic apparatus, the master controller can carry out predetermined control operations relative to the respective circuit blocks. During testing and/or adjustment, an auxiliary master control circuit is connected to the control bus lines in order to control the operational circuitry in place of the master control circuit, while holding the master control in the slave mode.

摘要翻译： 电子装置的数字控制系统采用内部总线系统，并且包括至少一个主控制器和经由控制总线连接的多个操作电路，使得在电子设备的正常操作期间，主控制器可以执行预定的控制操作 相对于各个电路块。 在测试和/或调整期间，辅助主控制电路连接到控制总线，以便在将主控制保持在从模式的同时控制操作电路代替主控制电路。

公开(公告)号：US4751574A

公开(公告)日：1988-06-14

申请号：US831875

申请日：1986-02-24

申请人： Takao Mogi ,  Masayuki Suematsu ,  Kosuke Fujita

发明人： Takao Mogi ,  Masayuki Suematsu ,  Kosuke Fujita

IPC分类号： H04L7/08 ,  H04L12/40 ,  H04N7/00 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N7/04

CPC分类号： H04N5/44

摘要： A control system for an electronic apparatus, such as a television receiver, having a control circuit with a control program in an internal memory sequentially communicates over an internal bus within predetermined intervals, such as within the vertical blanking interval of the television signal, with a plurality of controllable circuits in the television receiver, and the control circuit operates to select and communicate with a specific, selected one of the controllable circuits first, in each predetermined interval, with the remainder of the controllable circuits being subsequently communicated with in the remaining portion of the vertical blanking interval.

摘要翻译： 用于具有在内部存储器中具有控制程序的控制电路的诸如电视接收机的电子设备的控制系统通过内部总线按预定间隔（例如在电视信号的垂直消隐间隔内）顺序通信， 电视接收机中的多个可控电路，并且控制电路操作以在每个预定间隔中首先选择并与一个特定的所选可控电路进行通信，其余的可控电路随后在其余部分中通信 的垂直消隐间隔。

公开(公告)号：US4633313A

公开(公告)日：1986-12-30

申请号：US816831

申请日：1986-01-07

申请人： Takao Mogi ,  Masayuki Suematsu

发明人： Takao Mogi ,  Masayuki Suematsu

IPC分类号： H04N7/083 ,  H04B1/20 ,  H04N5/765 ,  H04N7/00 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N7/084 ,  H04N7/085 ,  H04N5/14

CPC分类号： H04B1/20 ,  H04N5/44 ,  H04N5/765

摘要： Digital data transfer in a digital television receiver between an internal central processing unit, or an external computer, and the video/audio processing circuitry by way of an internal bus is accomplished efficiently and without producing noise interference by using a high-frequency clock signal and a relatively low-frequency clock signal at different times. The high-frequency signal would normally produce visually perceptable noise, however, it is employed only during vertical blanking intervals, and the low-frequency clock signal, which would not produce visually perceptable noise, is used at all times other than the vertical blanking intervals, whereby noise interference that would be otherwise seen on the visual display of the television receiver is suppressed.

摘要翻译： 通过内部总线，在内部中央处理单元或外部计算机与视频/音频处理电路之间的数字电视接收机中进行数字数据传输，并且通过使用高频时钟信号而不产生噪声干扰， 在不同时间的相对低频时钟信号。 高频信号通常会产生视觉上可听见的噪声，但是仅在垂直消隐间隔期间使用，并且不会产生视觉上可感知噪声的低频时钟信号除了垂直消隐间隔之外的所有时间都被使用 从而抑制了在电视接收机的视觉显示器上另外看到的噪声干扰。

公开(公告)号：US4275354A

公开(公告)日：1981-06-23

申请号：US5021

申请日：1979-01-19

申请人： Masayuki Suematsu ,  Takao Mogi ,  Akira Taki

发明人： Masayuki Suematsu ,  Takao Mogi ,  Akira Taki

IPC分类号： H03G1/02 ,  H03G3/00 ,  H03G3/02 ,  H03G3/20 ,  H03J9/00 ,  H03K5/04 ,  H03K5/05 ,  H03K7/08 ,  H03K11/00 ,  H04N5/00

CPC分类号： H03K5/05 ,  H03G1/02 ,  H03G3/00 ,  H03G3/20 ,  H03J9/00 ,  H03K5/04

摘要： First and second counters in a pulse width modulating circuit, whose respective outputs determine the trailing and leading edges of a pulse width modulated signal, count input clock pulses at a constant speed. The number of the pulses applied to the second counter during a cycle relative to the number of the pulses applied to the first counter is increased or decreased by one in response to a modulating pulse to change the counting phase of the second counter thereby changing the width of the pulse width modulated signal. Gates freeze the phases of the two counters at minimum and maximum pulse widths of the pulse width modulated signal to avoid abrupt jumps from minimum to maximum or vice versa.

摘要翻译： 脉宽调制电路中的第一和第二计数器，其各自的输出确定脉冲宽度调制信号的后沿和前沿，以恒定速度计数输入时钟脉冲。 相对于施加到第一计数器的脉冲数的周期中施加到第二计数器的脉冲的数量响应于调制脉冲而增加或减少一个，以改变第二计数器的计数相位，从而改变宽度 的脉宽调制信号。 闸门以脉宽调制信号的最小和最大脉冲宽度冻结两个计数器的相位，以避免从最小到最大突然跳跃，反之亦然。

公开(公告)号：US4858006A

公开(公告)日：1989-08-15

申请号：US203165

申请日：1988-06-07

申请人： Masakazu Suzuki ,  Masayuki Suematsu ,  Yoshinori Komiya

发明人： Masakazu Suzuki ,  Masayuki Suematsu ,  Yoshinori Komiya

IPC分类号： H03J1/00 ,  H03J9/06 ,  H04N5/44 ,  H04N5/63 ,  H04N17/00

CPC分类号： H03J1/0033 ,  H04N5/44 ,  H03J9/06

摘要： In controlling an electronic apparatus, such as, a color television receiver, of the type having signal processing circuits which are individually adjustable in accordance with respective control signals provided by a microcomputer or central processing unit (CPU) in response to data corresponding to predetermined or standardized conditions of the adjustable circuits and which are stored in a non-volatile memory along with a secret code, operating keys selectively actuable to provide input data to the CPU for representing an externally applied code and, in a servicing mode of the receiver, for rewriting the data in the memory and thereby changing the standardized conditions of the adjustable circuits, and inner bus lines connecting the CPU to the adjustable circuits, the non-volatile memory and the operating keys; a standby power supply provides electric power to the CPU at a time when operating keys are actuated for inputting data representing an externally applied code to the CPU, a main power supply is turned on for supplying power to the adjustable circuits and thereby causing the receiver to display a color image, and the servicing mode of the receiver is established only when the externally applied code coincides with the stored secret code and the turning on of the main power supply is effected within a predetermined period after the externally applied code has been made to be coincident with the stored secret code.

摘要翻译： 在控制具有根据由微型计算机或中央处理单元（CPU）提供的相应控制信号单独调节的信号处理电路的类型的彩色电视接收机的响应于对应于预定的或 可调电路的标准化条件，以及与秘密码一起存储在非易失性存储器中的操作键，以便向CPU提供用于表示外部应用代码的输入数据，并且在接收机的服务模式中为 重写存储器中的数据，从而改变可调电路的标准化条件，以及将CPU连接到可调节电路的内部总线，非易失性存储器和操作键; 备用电源在CPU启动操作键时向CPU提供电力，以将表示外部施加的代码的数据输入到CPU，打开主电源以向可调节电路供电，从而使接收器 显示彩色图像，并且仅当外部施加的代码与存储的密码一致时才建立接收机的服务模式，并且在外部应用代码已经被制成之后的预定时间段内实现主电源的接通 与存储的密码相符。

公开(公告)号：US20080253692A1

公开(公告)日：2008-10-16

申请号：US12082625

申请日：2008-04-10

申请人： Masayuki Suematsu ,  Takayuki Ohe ,  Masato Usuki ,  Masanari Yamamoto ,  Kenkichi Kobayashi

发明人： Masayuki Suematsu ,  Takayuki Ohe ,  Masato Usuki ,  Masanari Yamamoto ,  Kenkichi Kobayashi

IPC分类号： G06K9/54

CPC分类号： H04N19/577 ,  H04N19/132 ,  H04N19/587 ,  H04N19/87

摘要： An image processing apparatus includes: a detecting unit configured to detect a motion vector from an input image signal acting as the image signal for each of chronologically input pixels; a determining unit configured to determine whether the input image signal in terms of a level meets a predetermined condition; and an interpolating unit configured such that if the input image signal is not found to meet the predetermined condition, then the interpolating unit interpolates and outputs an input image signal intermediate signal interposed at a predetermined point in time between the input image signal and a preceding input image signal that precedes the input image signal, in accordance with the motion vector, and if the input image signal is found to meet the predetermined condition, then the interpolating unit allows the input image signal to be output unchanged as the input image signal intermediate signal.

摘要翻译： 一种图像处理装置，包括：检测单元，被配置为从作为每个时间顺序输入像素的图像信号的输入图像信号中检测运动矢量; 确定单元，被配置为确定所述输入图像信号是否满足预定条件; 以及内插单元，被配置为使得如果没有发现输入图像信号满足预定条件，则内插单元插入并输出在输入图像信号和前一输入之间的预定时间点插入的输入图像信号中间信号 根据运动矢量在输入图像信号之前的图像信号，并且如果发现输入图像信号满足预定条件，则内插单元允许输入图像信号作为输入图像信号中间信号而不变地输出 。

公开(公告)号：US5841445A

公开(公告)日：1998-11-24

申请号：US666595

申请日：1996-06-18

申请人： Toshihiko Hamamatsu ,  Masayuki Suematsu ,  Makoto Kondo

发明人： Toshihiko Hamamatsu ,  Masayuki Suematsu ,  Makoto Kondo

IPC分类号： H04N5/262 ,  H04N5/45 ,  G06F13/00

CPC分类号： H04N5/2624 ,  H04N5/45

摘要： An image displaying apparatus comprises a line memory from which each line period segment of a first video signal is read during a half line period to produce a first half line period video signal segment, first and second field memories, from each of which each of line period segments contained in each odd or even field period portion of a second video signal is read during a half line period to produce a second or third half line period video signal segment, a signal selector operative to extract alternately the first and second half line period video signal segments to form a first field period video signal portion or extract alternately the first and third half line period video signal segments to form a second field period video signal portion, a dual image display portion for displaying double window picture images in response to the first and second field period video signal portions, an overtaking detector for detecting an overtaking reading condition possibly caused in the first and second field memories, and a writing and reading controller operative to control a timing for writing and reading of the field period portions in the first field memory and a timing for writing and reading of the field period portions in the second field memory so as to suppress defects of display resulting from the overtaking reading and appearing on the double window picture images displayed on the dual image display portion when the overtaking reading condition is detected by the overtaking detector.

摘要翻译： 图像显示装置包括行存储器，在半行周期期间从第一视频信号的每个行周期段读取第一半行周期视频信号段，第一和第二场存储器，其中每条行 在半行周期期间读取包含在第二视频信号的每个奇数或偶数场周期部分中的周期段，以产生第二或第三半行周期视频信号段，信号选择器可操作地交替地提取第一和第二半行周期 视频信号段以形成第一场周期视频信号部分或者交替地提取第一和第三半行周期视频信号段以形成第二场周期视频信号部分，双图像显示部分，用于响应于第二场周期视频信号部分显示双窗口图像图像 第一和第二场周期视频信号部分，用于检测可能在冷杉中引起的超车读取条件的超车检测器 第一和第二场存储器，以及写入和读取控制器，用于控制第一场存储器中的场周期部分的写入和读取的定时以及第二场存储器中的场周期部分的写入和读取的定时，以便 以便在超越检测器检测到超越读取条件时，抑制由于超越读取引起的显示的缺陷，并且出现在双重图像显示部分上显示的双窗口图像图像上。

公开(公告)号：US5537159A

公开(公告)日：1996-07-16

申请号：US246131

申请日：1994-05-19

申请人： Masayuki Suematsu ,  Toshihiko Hamamatsu ,  Makoto Kondo

发明人： Masayuki Suematsu ,  Toshihiko Hamamatsu ,  Makoto Kondo

IPC分类号： H04N5/74 ,  H04N3/233 ,  H04N9/28 ,  H04N9/31

CPC分类号： H04N9/28 ,  H04N3/2335

摘要： The nonlinear, deflection waveform used improve registration in a three picture tube projection television system is produced using interpolation of stored data setting points by first performing a reduced number of high-order interpolation calculations using the setting points and then performing low-order interpolation calculations either between two calculated high-order interpolated data points or between one of the calculated high-order interpolated data points and one of the setting points. This results in reducing the work load on the central processing unit in the registration system. In addition, a reduced bit-size requirement for the interpolation portion of the registration is obtained by storing registration data of a first bit size and then adding bits below the original LSB for the interpolation calculation prior to performing the digital to analog conversion.

摘要翻译： 所使用的非线性偏转波形，通过使用设定点首先进行减数次的高次插值计算，然后进行低阶插值计算，通过使用存储的数据设定点的插值来生成三像素投影电视系统的配准， 在两个计算的高阶内插数据点之间或者在所计算的高阶内插数据点之一和设定点之一之间。 这导致减少注册系统中的中央处理单元的工作负载。 此外，通过存储第一位大小的登记数据，然后在执行数模转换之前，将用于内插计算的原始LSB之下的位相加，来获得注册的插值部分的缩小比特大小要求。