公开(公告)号：US4843289A

公开(公告)日：1989-06-27

申请号：US161316

申请日：1988-02-23

申请人： Takao Mogi ,  Keiji Yuzawa ,  Yoshinori Komiya ,  Masayuki Suematsu ,  Fujio Tagami

发明人： Takao Mogi ,  Keiji Yuzawa ,  Yoshinori Komiya ,  Masayuki Suematsu ,  Fujio Tagami

IPC分类号： H04B1/20 ,  H04N5/44

CPC分类号： H04N5/44 ,  H04B1/205

摘要： Digitally controllable ICs or function blocks in an electronic apparatus are connected through control bus lines, and a switch device is provided for disconnecting one of the digitally controllable ICs or function blocks from the control bus so that the control bus is not disabled when that one IC is turned off or is not occupied when the IC is operating in its internal processing mode. Therefore, communication between the remaining ICs can be maintained through the control bus.

摘要翻译： 电子设备中的数字可控IC或功能块通过控制总线连接，并且提供开关装置用于将数字可控IC或功能块中的一个与控制总线断开，使得当该一个IC 当IC处于其内部处理模式时，它被关闭或不被占用。 因此，可以通过控制总线来保持剩余IC之间的通信。

公开(公告)号：US4751574A

公开(公告)日：1988-06-14

申请号：US831875

申请日：1986-02-24

申请人： Takao Mogi ,  Masayuki Suematsu ,  Kosuke Fujita

发明人： Takao Mogi ,  Masayuki Suematsu ,  Kosuke Fujita

IPC分类号： H04L7/08 ,  H04L12/40 ,  H04N7/00 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N7/04

CPC分类号： H04N5/44

摘要： A control system for an electronic apparatus, such as a television receiver, having a control circuit with a control program in an internal memory sequentially communicates over an internal bus within predetermined intervals, such as within the vertical blanking interval of the television signal, with a plurality of controllable circuits in the television receiver, and the control circuit operates to select and communicate with a specific, selected one of the controllable circuits first, in each predetermined interval, with the remainder of the controllable circuits being subsequently communicated with in the remaining portion of the vertical blanking interval.

摘要翻译： 用于具有在内部存储器中具有控制程序的控制电路的诸如电视接收机的电子设备的控制系统通过内部总线按预定间隔（例如在电视信号的垂直消隐间隔内）顺序通信， 电视接收机中的多个可控电路，并且控制电路操作以在每个预定间隔中首先选择并与一个特定的所选可控电路进行通信，其余的可控电路随后在其余部分中通信 的垂直消隐间隔。

公开(公告)号：US4633313A

公开(公告)日：1986-12-30

申请号：US816831

申请日：1986-01-07

申请人： Takao Mogi ,  Masayuki Suematsu

发明人： Takao Mogi ,  Masayuki Suematsu

IPC分类号： H04N7/083 ,  H04B1/20 ,  H04N5/765 ,  H04N7/00 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N7/084 ,  H04N7/085 ,  H04N5/14

CPC分类号： H04B1/20 ,  H04N5/44 ,  H04N5/765

摘要： Digital data transfer in a digital television receiver between an internal central processing unit, or an external computer, and the video/audio processing circuitry by way of an internal bus is accomplished efficiently and without producing noise interference by using a high-frequency clock signal and a relatively low-frequency clock signal at different times. The high-frequency signal would normally produce visually perceptable noise, however, it is employed only during vertical blanking intervals, and the low-frequency clock signal, which would not produce visually perceptable noise, is used at all times other than the vertical blanking intervals, whereby noise interference that would be otherwise seen on the visual display of the television receiver is suppressed.

摘要翻译： 通过内部总线，在内部中央处理单元或外部计算机与视频/音频处理电路之间的数字电视接收机中进行数字数据传输，并且通过使用高频时钟信号而不产生噪声干扰， 在不同时间的相对低频时钟信号。 高频信号通常会产生视觉上可听见的噪声，但是仅在垂直消隐间隔期间使用，并且不会产生视觉上可感知噪声的低频时钟信号除了垂直消隐间隔之外的所有时间都被使用 从而抑制了在电视接收机的视觉显示器上另外看到的噪声干扰。

公开(公告)号：US4275354A

公开(公告)日：1981-06-23

申请号：US5021

申请日：1979-01-19

申请人： Masayuki Suematsu ,  Takao Mogi ,  Akira Taki

发明人： Masayuki Suematsu ,  Takao Mogi ,  Akira Taki

IPC分类号： H03G1/02 ,  H03G3/00 ,  H03G3/02 ,  H03G3/20 ,  H03J9/00 ,  H03K5/04 ,  H03K5/05 ,  H03K7/08 ,  H03K11/00 ,  H04N5/00

CPC分类号： H03K5/05 ,  H03G1/02 ,  H03G3/00 ,  H03G3/20 ,  H03J9/00 ,  H03K5/04

摘要： First and second counters in a pulse width modulating circuit, whose respective outputs determine the trailing and leading edges of a pulse width modulated signal, count input clock pulses at a constant speed. The number of the pulses applied to the second counter during a cycle relative to the number of the pulses applied to the first counter is increased or decreased by one in response to a modulating pulse to change the counting phase of the second counter thereby changing the width of the pulse width modulated signal. Gates freeze the phases of the two counters at minimum and maximum pulse widths of the pulse width modulated signal to avoid abrupt jumps from minimum to maximum or vice versa.

摘要翻译： 脉宽调制电路中的第一和第二计数器，其各自的输出确定脉冲宽度调制信号的后沿和前沿，以恒定速度计数输入时钟脉冲。 相对于施加到第一计数器的脉冲数的周期中施加到第二计数器的脉冲的数量响应于调制脉冲而增加或减少一个，以改变第二计数器的计数相位，从而改变宽度 的脉宽调制信号。 闸门以脉宽调制信号的最小和最大脉冲宽度冻结两个计数器的相位，以避免从最小到最大突然跳跃，反之亦然。

公开(公告)号：US4805085A

公开(公告)日：1989-02-14

申请号：US203616

申请日：1988-06-06

申请人： Takao Mogi ,  Masayuki Suematsu

发明人： Takao Mogi ,  Masayuki Suematsu

IPC分类号： G05B15/02 ,  G05B19/042 ,  G06F13/20 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177 ,  G06F15/46 ,  G06F11/16

CPC分类号： G05B19/0421

摘要： A digital control system for electronic apparatus employs an internal bus system and includes at least one master controller and a plurality of operational circuits connected via control bus lines so that, during normal operation of the electronic apparatus, the master controller can carry out predetermined control operations relative to the respective circuit blocks. During testing and/or adjustment, an auxiliary master control circuit is connected to the control bus lines in order to control the operational circuitry in place of the master control circuit, while holding the master control in the slave mode.

摘要翻译： 电子装置的数字控制系统采用内部总线系统，并且包括至少一个主控制器和经由控制总线连接的多个操作电路，使得在电子设备的正常操作期间，主控制器可以执行预定的控制操作 相对于各个电路块。 在测试和/或调整期间，辅助主控制电路连接到控制总线，以便在将主控制保持在从模式的同时控制操作电路代替主控制电路。

公开(公告)号：US4743968A

公开(公告)日：1988-05-10

申请号：US831876

申请日：1986-02-24

申请人： Takao Mogi ,  Masayuki Suematsu ,  Kosuke Fujita

发明人： Takao Mogi ,  Masayuki Suematsu ,  Kosuke Fujita

IPC分类号： H04L12/40 ,  H04N7/00 ,  H04N5/44

CPC分类号： H04N5/44

摘要： A system for controlling electronic apparatus, such as a television receiver, which employs a control circuit having a control program in a read only memory to sequentially communicate over an internal system bus in a predetermined interval with a plurality of controllable, operational circuit blocks forming the electronic apparatus, in which the control circuit selects a specific circuit block for data transfer upon a request signal. In one embodiment, a request signal is transmitted prior to a vertical blanking interval in a television signal and in another embodiment, a dedicated line is provided from a selected controllable unit to the control unit, whereby the request signal can be transmitted at any time, irrespective of whether data is being transferred at such time.

摘要翻译： 一种用于控制诸如电视接收机的电子设备的系统，其采用具有在只读存储器中的控制程序的控制电路，以在预定间隔内通过内部系统总线顺序地与多个可控的操作电路块形成 电子设备，其中控制电路根据请求信号选择用于数据传输的特定电路块。 在一个实施例中，在电视信号中的垂直消隐间隔之前发送请求信号，在另一个实施例中，从所选择的可控单元向控制单元提供专用线路，从而可以随时发送请求信号， 无论数据是否在此时传输。

公开(公告)号：US4810958A

公开(公告)日：1989-03-07

申请号：US86233

申请日：1987-08-17

申请人： Takao Mogi ,  Masahiko Morizono

发明人： Takao Mogi ,  Masahiko Morizono

IPC分类号： G06F13/10 ,  G06F11/273 ,  H04N17/04 ,  G01R31/28

CPC分类号： H04N17/04 ,  G06F11/273

摘要： An arrangement and a method for testing various kinds of electronic equipment, each having an internal bus, during assembly and during subsequent servicing, wherein a plurality of software packages, each storing instructions and data pertinent to the testing and adjustment of a specific kind of equipment are prepared and a computer is connectable in common to the various kinds of equipment via their internal buses for testing any one of the various equipments according to the contents of the appropriate software package.

摘要翻译： 一种用于测试各种电子设备的装置和方法，每种电子设备具有内部总线，组装期间和后续维护期间，其中多个软件包，每个存储与特定类型的设备的测试和调整有关的指令和数据 并且计算机可以通过其内部总线通用于各种设备，以根据适当软件包的内容测试各种设备中的任何一个。

公开(公告)号：US4635113A

公开(公告)日：1987-01-06

申请号：US626155

申请日：1984-06-29

申请人： Takashi Okada ,  Takao Mogi ,  Shoji Ohmori ,  Yutaka Tanaka ,  Hiroyuki Kobayashi

发明人： Takashi Okada ,  Takao Mogi ,  Shoji Ohmori ,  Yutaka Tanaka ,  Hiroyuki Kobayashi

IPC分类号： G06F21/10 ,  H04N7/167 ,  H04N7/171

CPC分类号： H04N7/1716 ,  H04N7/1675

摘要： This invention relates to an apparatus for descrambling scrambled television signals including a scrambled video signal having a first scrambling pattern, a scrambled control signal having a second scrambling pattern, and descrambling signals.

摘要翻译： 本发明涉及一种用于解扰加扰电视信号的装置，包括具有第一加扰模式的加扰视频信号，具有第二加扰模式的加扰控制信号和解扰信号。

公开(公告)号：US4471377A

公开(公告)日：1984-09-11

申请号：US519222

申请日：1983-08-03

申请人： Takao Mogi ,  Satoru Maeda

发明人： Takao Mogi ,  Satoru Maeda

IPC分类号： H04N7/08 ,  G09G5/02 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/081 ,  H04N9/00 ,  H04N9/535

CPC分类号： G09G5/02

摘要： A color information display apparatus includes a common memory of an integrated circuit configuration for storing both pattern data and color data describing an attribute of the corresponding pattern data to be displayed on a CRT, the common memory including a first address area for the pattern data and a second, different address area for the color data, a circuit for generating address signals for the common memories in response to the scanning position of the electron beam on the screen of the CRT, a parallel-serial converting circuit for converting parallel pattern data in the common memory to serial data, a first latch circuit for latching the color data in the common memory to produce an output color signal, a circuit for generating a color information signal from the serial data from the parallel-serial converting circuit and the output signal from the first latch circuit, an address selector connected between the address signal generating circuit and the common memory, the first address area and the second address area of the common memory being addressed alternatively by the address selector, and a second latch circuit connected between the common memory and the serial-parallel converting circuit for latching the pattern data supplied to the latter circuit.

摘要翻译： 彩色信息显示装置包括集成电路配置的公共存储器，用于存储描述要在CRT上显示的相应图案数据的属性的图案数据和颜色数据，所述公共存储器包括用于图案数据的第一地址区域和 用于彩色数据的第二不同的地址区域，用于响应CRT上的电子束的扫描位置产生公共存储器的地址信号的电路，用于转换CRT的屏幕上的并行图案数据的并行串行转换电路 串行数据的公共存储器，用于将公共存储器中的颜色数据锁存以产生输出彩色信号的第一锁存电路，用于从并行串行转换电路的串行数据产生颜色信息信号的电路和输出信号 连接在地址信号发生电路和公共存储器之间的地址选择器从第一锁存电路开始， t地址区域和公共存储器的第二地址区域由地址选择器交替地寻址;以及第二锁存电路，连接在公共存储器和串行 - 并行转换电路之间，用于锁存提供给后一电路的模式数据。

公开(公告)号：US4439787A

公开(公告)日：1984-03-27

申请号：US349651

申请日：1982-02-17

申请人： Takao Mogi ,  Kouji Morita ,  Osamu Matsunaga

发明人： Takao Mogi ,  Kouji Morita ,  Osamu Matsunaga

IPC分类号： H03J7/02 ,  H04N5/50

CPC分类号： H03J7/02 ,  H04N5/50

摘要： An AFT circuit for a television receiver automatically adjusts the frequency of a tuner local oscillator, not only on the basis of an error signal provided from an AFT discriminator, but also on the basis of horizontal synchronizing pulses contained in the video signal to which the receiver is tuned. A synch signal detector detects the presence or absence of the synchronizing pulses. A control circuit provides a control signal to the local oscillator in response to the AFT error signal when the latter is above or below a reference voltage such that the desired frequency is within an AFT capture range. However, when the AFT signal is at the reference voltage, the control circuit provides the control signal based on the presence or absence of the synchronizing pulses, such that when the pulses are present, the local oscillator frequency is raised, but when the pulses are absent, the local oscillator frequency is lowered. Then, when the AFT signal is present, the local oscillator is controlled thereby. This AFT circuit has an expanded effective capture range, and is prevented from locking onto the sound carrier of an adjacent channel. 00202

摘要翻译： 用于电视接收机的AFT电路不仅基于从AFT鉴频器提供的误差信号，而且还基于包含在接收机的视频信号中的水平同步脉冲自动调节调谐器本地振荡器的频率 被调整 同步信号检测器检测同步脉冲的存在或不存在。 当控制电路高于或低于参考电压时，控制电路响应于AFT误差信号向本地振荡器提供控制信号，使得期望的频率在AFT捕获范围内。 然而，当AFT信号处于参考电压时，控制电路基于同步脉冲的存在或不存在来提供控制信号，使得当脉冲存在时，本地振荡器频率升高，但是当脉冲为 不存在，本地振荡器频率降低。 然后，当存在AFT信号时，由此控制本地振荡器。 这个AFT