公开(公告)号：US08980289B2

公开(公告)日：2015-03-17

申请号：US13819262

申请日：2011-05-26

申请人： Takashi Hara ,  Yuki Higuchi ,  Mikio Fujii

发明人： Takashi Hara ,  Yuki Higuchi ,  Mikio Fujii

IPC分类号： A61K45/00 ,  A61K39/02 ,  A61K39/00 ,  A61K39/38 ,  A61K47/00 ,  A01N63/00 ,  A01N65/00 ,  A23L1/30

CPC分类号： A61K35/747 ,  A23L33/135

摘要： The purpose of the present invention is to provide a better intestine immunomodulator. The intestine immunomodulator of the present invention comprises bacterial cells or a bacterial component of a Lactobacillus paracasei K71 strain having an international deposit No.: FERM BP-11098 as an active ingredient. Preferably, the intestine immunomodulator is used to facilitate production of secretory immunoglobulin A or to activate natural killer cells.

摘要翻译： 本发明的目的是提供一种更好的肠免疫调节剂。 本发明的肠内免疫调节剂包含具有国际保藏号：FERM BP-11098的细菌细胞或副干酪乳杆菌K71菌株的细菌成分作为活性成分。 优选地，肠免疫调节剂用于促进分泌型免疫球蛋白A的产生或激活天然杀伤细胞。

公开(公告)号：US20130224252A1

公开(公告)日：2013-08-29

申请号：US13819262

申请日：2011-05-26

申请人： Takashi Hara ,  Yuki Higuchi ,  Mikio Fujii

发明人： Takashi Hara ,  Yuki Higuchi ,  Mikio Fujii

IPC分类号： A61K35/74 ,  A23L1/30

CPC分类号： A61K35/747 ,  A23L33/135

摘要： The purpose of the present invention is to provide a better intestine immunomodulator. The intestine immunomodulator of the present invention comprises bacterial cells or a bacterial component of a Lactobacillus paracasei K71 strain having an international deposit No.: FERM BP-11098 as an active ingredient. Preferably, the intestine immunomodulator is used to facilitate production of secretory immunoglobulin A or to activate natural killer cells.

摘要翻译： 本发明的目的是提供一种更好的肠免疫调节剂。 本发明的肠内免疫调节剂包含具有国际保藏号：FERM BP-11098的细菌细胞或副干酪乳杆菌K71菌株的细菌成分作为活性成分。 优选地，肠免疫调节剂用于促进分泌型免疫球蛋白A的产生或激活天然杀伤细胞。

公开(公告)号：US08174290B2

公开(公告)日：2012-05-08

申请号：US12912348

申请日：2010-10-26

申请人： Yuki Higuchi

发明人： Yuki Higuchi

IPC分类号： G01R29/02 ,  H03B1/00

CPC分类号： H03K5/1252

摘要： A noise reduction circuit includes first and second reset signal generation circuits that generate first and second reset signals that are activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high level or a low level is maintained, and first and second counter circuits that count an inverted signal of the clock signal, and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit that includes a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock, wherein the selector circuit selects and outputs any of: a signal fixed at a high level or a low level, and an output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

摘要翻译： 噪声降低电路包括产生第一和第二复位信号的第一和第二复位信号产生电路，当第一和第二复位信号在数据输入信号变为低电平或高电平时被激活，并且当高电平或高电平时与时钟信号同步地停用 保持低电平，第一和第二计数器电路对时钟信号的反相信号进行计数，并由第一或第二复位信号复位。 噪声降低电路还包括数据输出电路，其包括选择器电路和输出触发器电路，输出触发电路与时钟同步地输出由选择器电路选择的信号，其中选择器电路选择并输出以下信号：固定信号 根据第一和第二计数器电路的输出信号的逻辑电平，输出触发电路的输出信号为高电平或低电平。

公开(公告)号：US09026833B2

公开(公告)日：2015-05-05

申请号：US13408280

申请日：2012-02-29

申请人： Yuki Higuchi

发明人： Yuki Higuchi

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  H03K5/04 ,  H03K7/08 ,  H03K5/00

CPC分类号： H03K5/04 ,  G11C7/22 ,  H03K7/08 ,  H03K2005/00293

摘要： In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence.

摘要翻译： 为了减少由电源噪声引起的数字信号的提取误差的发生，提供了一种设置有用于根据脉冲控制信号和数字信号保持电路执行开关操作的开关电路的半导体器件 用于取数字信号。 数字信号保持电路包括一个屏蔽信号产生电路，用于从脉冲控制信号产生一个屏蔽信号，该屏蔽信号用于保持数字信号在由切换引起的电源噪声发生的时间周期内被取出 在电源噪声发生的时间段期间，在电源噪声不发生的时间段期间取出数字信号时，不会取出数字信号。

公开(公告)号：US10263714B2

公开(公告)日：2019-04-16

申请号：US15623973

申请日：2017-06-15

申请人： Kazunori Aoki ,  Takayuki Awano ,  Yuki Higuchi

发明人： Kazunori Aoki ,  Takayuki Awano ,  Yuki Higuchi

IPC分类号： H04W24/06 ,  H04B17/15 ,  H04W76/25 ,  H04B17/10

摘要： According to one embodiment, a mobile terminal testing device which tests a mobile terminal including a plurality of transmitting antennas by transmitting/receiving radio signals between the mobile terminal testing device and the mobile terminal, includes a radio signal processing module configured to transmit and receive radio signals to and from the mobile terminal and a controller configured to cause the mobile terminal to switch one from another among the plurality of transmitting antennas by a predetermined radio signal transmitted to the mobile terminal via the radio signal processing module.

公开(公告)号：US20170366282A1

公开(公告)日：2017-12-21

申请号：US15623973

申请日：2017-06-15

申请人： Kazunori Aoki ,  Takayuki Awano ,  Yuki Higuchi

发明人： Kazunori Aoki ,  Takayuki Awano ,  Yuki Higuchi

IPC分类号： H04B17/15 ,  H04W76/04

CPC分类号： H04B17/15 ,  H04B17/102 ,  H04W76/25

摘要： According to one embodiment, a mobile terminal testing device which tests a mobile terminal including a plurality of transmitting antennas by transmitting/receiving radio signals between the mobile terminal testing device and the mobile terminal, includes a radio signal processing module configured to transmit and receive radio signals to and from the mobile terminal and a controller configured to cause the mobile terminal to switch one from another among the plurality of transmitting antennas by a predetermined radio signal transmitted to the mobile terminal via the radio signal processing module.

公开(公告)号：US08390332B2

公开(公告)日：2013-03-05

申请号：US13438530

申请日：2012-04-03

申请人： Yuki Higuchi

发明人： Yuki Higuchi

IPC分类号： G01R29/02 ,  H03B1/00

CPC分类号： H03K5/1252

摘要： Noise reduction circuit includes first and second reset signal generation circuits generating first and second reset signals activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high or low level is maintained, and first and second counter circuits that count an inverted signal of clock signal and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit including a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock. The selector circuit selects and outputs any of: signal fixed at a high level or low level, and output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

摘要翻译： 降噪电路包括当数据输入信号变为低电平或高电平时激活的第一和第二复位信号的第一和第二复位信号产生电路，并且当保持高电平或低电平时与时钟信号同步地被去激活， 以及第一和第二计数器电路，其对时钟信号的反相信号进行计数，并由第一或第二复位信号复位。 噪声降低电路还包括数据输出电路，该数据输出电路包括选择器电路和输出触发器电路，其输出与时钟同步的由选择器电路选择的信号。 选择器电路根据第一和第二计数器电路的输出信号的逻辑电平选择并输出固定为高电平或低电平的信号和输出触发器电路的输出信号。

公开(公告)号：US20090200875A1

公开(公告)日：2009-08-13

申请号：US12320881

申请日：2009-02-06

申请人： Yuki Higuchi

发明人： Yuki Higuchi

IPC分类号： H01H83/00 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78 ,  Y10T307/826

摘要： A semiconductor integrated circuit device includes: a first power supply region, power supply to which is controlled; and a second power supply region connected with a first power supply region. The first power supply region includes: a floating preventing circuit configured to fix an output voltage from the first power supply region to the second power supply region to a ground voltage in synchronization with stop of power supply.

摘要翻译： 一种半导体集成电路器件，包括：第一电源区域，被控制的电源; 以及与第一电源区域连接的第二电源区域。 第一电源区域包括：浮动防止电路，被配置为与电源停止同步地将来自第一电源区域的输出电压固定到第二电源区域到地电压。