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    Manufacturing method of thin film transistor including low resistance conductive thin films
    1.
    发明授权
    Manufacturing method of thin film transistor including low resistance conductive thin films 有权
    包括低电阻导电薄膜的薄膜晶体管的制造方法

    公开(公告)号：US07981734B2

    公开(公告)日：2011-07-19

    申请号：US12499559

    申请日：2009-07-08

    申请人： Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

    发明人： Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

    IPC分类号： H01L21/302

    CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618

    摘要： A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

    摘要翻译： 薄膜晶体管的制造方法包括在基板上形成一对源极/漏极，使得源极/漏极在其间限定间隙; 在源/漏电极上形成限定它们之间的间隙的低电阻导电薄膜; 以及在低电阻导电薄膜的上表面和限定在低电阻导电薄膜之间的间隙中形成氧化物半导体薄膜层，使得氧化物半导体薄膜层用作沟道。 蚀刻低电阻导电薄膜和氧化物半导体薄膜层，使得电阻导电薄膜的侧表面和氧化物半导体薄膜层的相应侧表面在沟道的沟道宽度方向上彼此重合。 栅电极安装在氧化物半导体薄膜层上。

    MANUFACTURING METHOD OF THIN FILM TRANSISTOR INCLUDING LOW RESISTANCE CONDUCTIVE THIN FILMS
    6.
    发明申请
    MANUFACTURING METHOD OF THIN FILM TRANSISTOR INCLUDING LOW RESISTANCE CONDUCTIVE THIN FILMS 有权
    具有低电阻导电薄膜的薄膜晶体管的制造方法

    公开(公告)号：US20090269881A1

    公开(公告)日：2009-10-29

    申请号：US12499559

    申请日：2009-07-08

    申请人： Mamoru FURUTA ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

    发明人： Mamoru FURUTA ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618

    摘要： A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

    摘要翻译： 薄膜晶体管的制造方法包括在基板上形成一对源极/漏极，使得源极/漏极在其间限定间隙; 在源/漏电极上形成限定它们之间的间隙的低电阻导电薄膜; 以及在低电阻导电薄膜的上表面和限定在低电阻导电薄膜之间的间隙中形成氧化物半导体薄膜层，使得氧化物半导体薄膜层用作沟道。 蚀刻低电阻导电薄膜和氧化物半导体薄膜层，使得电阻导电薄膜的侧表面和氧化物半导体薄膜层的相应侧表面在沟道的沟道宽度方向上彼此重合。 栅电极安装在氧化物半导体薄膜层上。

    Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error
    10.
    发明授权
    Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error 失效
    包括晶体管的半导体集成电路，其具有形成在元件隔离区域外部的扩散层，以防止软错误

    公开(公告)号：US08471336B2

    公开(公告)日：2013-06-25

    申请号：US13437311

    申请日：2012-04-02

    申请人： Hiroshi Furuta ,  Shouzou Uchida ,  Muneaki Matsushige ,  Junji Monden

    发明人： Hiroshi Furuta ,  Shouzou Uchida ,  Muneaki Matsushige ,  Junji Monden

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0207 ,  H01L27/0921 ,  H01L29/0653

    摘要： A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.

    摘要翻译： 半导体集成电路器件包括：P沟道MISFET（金属 - 绝缘体 - 半导体场效应晶体管）和N沟道MISFET中的至少一个的栅极电极，其设置在与阱隔离边界相位方向平行的方向上 在所述P沟道MISFET和所述N沟道MISFET之间的第一扩散层具有与设置在两个区域中的多个MISFET中的一个的漏极扩散层相同的导电类型的第一扩散层， MISFET，其分别在与栅电极正交的方向上分离，第二扩散层的导电类型与漏极扩散层的漏极扩散层的导电类型不同，所述漏极扩散层设置在阱隔离边界相之间 以及源极扩散层和漏极扩散层中的一个。