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公开(公告)号：US07446614B2
公开(公告)日：2008-11-04
申请号：US11403968
申请日：2006-04-14
申请人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
发明人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
CPC分类号： H03L7/18 , H03K19/0027 , H03L7/0995 , H03L7/23
摘要： A logical level converter generates an output signal by which a succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.
摘要翻译： 逻辑电平转换器产生输出信号，即使存在阈值波动因子，后续逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 将来自阈值可变逆变器的另一输出信号的直流分量输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。
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公开(公告)号：US20090096540A1
公开(公告)日：2009-04-16
申请号：US12243553
申请日：2008-10-01
申请人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
发明人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
IPC分类号： H03L7/085
CPC分类号： H03L7/18 , H03K19/0027 , H03L7/0995 , H03L7/23
摘要： A logical level converter generates an output signal by which a logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.
摘要翻译： 逻辑电平转换器产生输出信号，由此即使存在阈值波动因子，逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 来自阈值可变逆变器的另一输出信号的DC分量被输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。
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公开(公告)号：US20060261873A1
公开(公告)日：2006-11-23
申请号：US11403968
申请日：2006-04-14
申请人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
发明人： Takashi Kawamoto , Masaru Kokubo , Takashi Oshima
IPC分类号： H03K12/00
CPC分类号： H03L7/18 , H03K19/0027 , H03L7/0995 , H03L7/23
摘要： A logical level converter generates an output signal by which succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.
摘要翻译： 逻辑电平转换器产生输出信号，即使存在阈值波动因子，后续逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 来自阈值可变逆变器的另一输出信号的DC分量被输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。
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4.发明申请Phase locked loop circuit and semiconductor integrated circuit device using the same 有权锁相环电路和使用其的半导体集成电路器件公开(公告)号：US20070030079A1
公开(公告)日：2007-02-08
申请号：US11488866
申请日：2006-07-19
申请人： Takashi Kawamoto , Masaru Kokubo
发明人： Takashi Kawamoto , Masaru Kokubo
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/1976 , H03L2207/06
摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.
摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。
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5.发明授权Phase locked loop circuit and semiconductor integrated circuit device using the same 有权锁相环电路和使用其的半导体集成电路器件公开(公告)号：US07504894B2
公开(公告)日：2009-03-17
申请号：US11488866
申请日：2006-07-19
申请人： Takashi Kawamoto , Masaru Kokubo
发明人： Takashi Kawamoto , Masaru Kokubo
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03L7/1976 , H03L2207/06
摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.
摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。
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6.发明授权Phase Locked loop circuit and semiconductor integrated circuit device using the same 有权锁相环电路和使用其的半导体集成电路器件公开(公告)号：US07737792B2
公开(公告)日：2010-06-15
申请号：US12362486
申请日：2009-01-29
申请人： Takashi Kawamoto , Masaru Kokubo
发明人： Takashi Kawamoto , Masaru Kokubo
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03L7/1976 , H03L2207/06
摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.
摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。
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7.发明申请PHASE LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING THE SAME 有权使用相位锁相环电路和半导体集成电路装置公开(公告)号：US20090153204A1
公开(公告)日：2009-06-18
申请号：US12362486
申请日：2009-01-29
申请人： Takashi Kawamoto , Masaru Kokubo
发明人： Takashi Kawamoto , Masaru Kokubo
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03L7/1976 , H03L2207/06
摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.
摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。
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8.发明授权公开(公告)号：US07957710B2
公开(公告)日：2011-06-07
申请号：US12216092
申请日：2008-06-30
CPC分类号： H03F1/0227 , H03F1/0205 , H03F1/32 , H03F3/24 , H03F2200/102 , H03F2200/99
摘要： A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.
摘要翻译： DCDC转换器包括将输入信号分解为N个信号分量的信号分离单元; N个DCDC转换器元件，分别处理N个分离信号; 以及加法器，其添加来自多个DCDC转换器元件的输出以产生输出信号。 每个DCDC转换器元件具有比输入信号的适用频带窄的操作频带，并且选择允许DCDC转换器元件的转换效率针对适用频带的任何频带进行优化的设计参数。 例如，配置反相器的PMOS晶体管和NMOS晶体管的参数被设计为优化任何频带处的效率。 输入信号的频带被分离，并且每个分离输出被输入到具有对应的频率和高效率特性的DCDC转换器元件。
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9.发明申请公开(公告)号：US20090011728A1
公开(公告)日：2009-01-08
申请号：US12216092
申请日：2008-06-30
CPC分类号： H03F1/0227 , H03F1/0205 , H03F1/32 , H03F3/24 , H03F2200/102 , H03F2200/99
摘要： A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.
摘要翻译： DCDC转换器包括将输入信号分解为N个信号分量的信号分离单元; N个DCDC转换器元件，分别处理N个分离信号; 以及加法器，其添加来自多个DCDC转换器元件的输出以产生输出信号。 每个DCDC转换器元件具有比输入信号的适用频带窄的操作频带，并且选择允许DCDC转换器元件的转换效率针对适用频带的任何频带进行优化的设计参数。 例如，配置反相器的PMOS晶体管和NMOS晶体管的参数被设计为优化任何频带处的效率。 输入信号的频带被分离，并且每个分离输出被输入到具有对应的频率和高效率特性的DCDC转换器元件。
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10.发明授权Jointing structure of vehicle traveling path joints having expansion function and method of mounting elastic member therein 有权具有膨胀功能的车辆行驶路径接头的接合结构和其中安装弹性构件的方法公开(公告)号：US08602678B2
公开(公告)日：2013-12-10
申请号：US13413931
申请日：2012-03-07
申请人： Takashi Kawamoto , Takafumi Matsuda , Masaaki Miyamoto , Hironori Sadakane , Katsunori Yokokawa , Minoru Tsukahara , Junichi Kawaura , Yuki Motoyama
发明人： Takashi Kawamoto , Takafumi Matsuda , Masaaki Miyamoto , Hironori Sadakane , Katsunori Yokokawa , Minoru Tsukahara , Junichi Kawaura , Yuki Motoyama
IPC分类号： E01C11/02
CPC分类号： E01D19/06
摘要： A jointing structure comprising multiple steps provided face to face at the coaxially built traveling path ends with an expansion gap between, multiple elastic members respectively mounted inside the multiple steps, and a joint block mounted on the multiple elastic members across the expansion gap. Multiple supporting blocks and one or more than one intermediate joint block are mounted inside the multiple steps with the joint block between. The multiple supporting blocks, the joint block and the one or more than one intermediate joint block are of concrete. The elastic members are joined together across the expansion gap. The elastic member on one side is fixed to the inside of the step on one side and then subjected to deformation toward the bridge girder axis, and thereafter, the elastic member on the other side is fixed to the inside of the step on the other side.
摘要翻译： 包括在同轴构造的行进路径上面对面设置的多个台阶的接合结构，分别安装在多个台阶内的多个弹性构件之间的膨胀间隙，以及安装在多个弹性构件上的膨胀间隙的接头块。 多个支撑块和一个或多于一个中间接合块安装在多个台阶内，其间具有接合块。 多个支撑块，接头块和一个或多个中间接头块是具体的。 弹性构件通过膨胀间隙连接在一起。 一侧的弹性部件固定在一侧的台阶的内侧，然后朝向桥梁轴线变形，此后，另一侧的弹性部件固定在台阶的另一侧的内侧 。
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