公开(公告)号：US20070030079A1

公开(公告)日：2007-02-08

申请号：US11488866

申请日：2006-07-19

申请人： Takashi Kawamoto ,  Masaru Kokubo

发明人： Takashi Kawamoto ,  Masaru Kokubo

IPC分类号： H03L7/00

CPC分类号： H03L7/0995 ,  H03L7/1976 ,  H03L2207/06

摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.

摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。

公开(公告)号：US07446614B2

公开(公告)日：2008-11-04

申请号：US11403968

申请日：2006-04-14

申请人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

发明人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

IPC分类号： H03L7/085 ,  H03L7/089 ,  H03L7/099

CPC分类号： H03L7/18 ,  H03K19/0027 ,  H03L7/0995 ,  H03L7/23

摘要： A logical level converter generates an output signal by which a succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

摘要翻译： 逻辑电平转换器产生输出信号，即使存在阈值波动因子，后续逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 将来自阈值可变逆变器的另一输出信号的直流分量输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

公开(公告)号：US20090096540A1

公开(公告)日：2009-04-16

申请号：US12243553

申请日：2008-10-01

申请人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

发明人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

IPC分类号： H03L7/085

CPC分类号： H03L7/18 ,  H03K19/0027 ,  H03L7/0995 ,  H03L7/23

摘要： A logical level converter generates an output signal by which a logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

摘要翻译： 逻辑电平转换器产生输出信号，由此即使存在阈值波动因子，逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 来自阈值可变逆变器的另一输出信号的DC分量被输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

公开(公告)号：US07504894B2

公开(公告)日：2009-03-17

申请号：US11488866

申请日：2006-07-19

申请人： Takashi Kawamoto ,  Masaru Kokubo

发明人： Takashi Kawamoto ,  Masaru Kokubo

IPC分类号： H03L7/08

CPC分类号： H03L7/0995 ,  H03L7/1976 ,  H03L2207/06

摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.

摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。

公开(公告)号：US07737792B2

公开(公告)日：2010-06-15

申请号：US12362486

申请日：2009-01-29

申请人： Takashi Kawamoto ,  Masaru Kokubo

发明人： Takashi Kawamoto ,  Masaru Kokubo

IPC分类号： H03L7/08

CPC分类号： H03L7/0995 ,  H03L7/1976 ,  H03L2207/06

摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.

摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。

公开(公告)号：US20090153204A1

公开(公告)日：2009-06-18

申请号：US12362486

申请日：2009-01-29

申请人： Takashi Kawamoto ,  Masaru Kokubo

发明人： Takashi Kawamoto ,  Masaru Kokubo

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  H03L7/1976 ,  H03L2207/06

摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.

摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。

公开(公告)号：US20060261873A1

公开(公告)日：2006-11-23

申请号：US11403968

申请日：2006-04-14

申请人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

发明人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

IPC分类号： H03K12/00

CPC分类号： H03L7/18 ,  H03K19/0027 ,  H03L7/0995 ,  H03L7/23

摘要： A logical level converter generates an output signal by which succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

摘要翻译： 逻辑电平转换器产生输出信号，即使存在阈值波动因子，后续逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 来自阈值可变逆变器的另一输出信号的DC分量被输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

公开(公告)号：US20120155301A1

公开(公告)日：2012-06-21

申请号：US13308635

申请日：2011-12-01

申请人： Masayuki MIYAZAKI ,  Kenichi Mizugaki ,  Masaru Kokubo ,  Hideyuki Nagaishi ,  Nobuhisa Kobayashi

发明人： Masayuki MIYAZAKI ,  Kenichi Mizugaki ,  Masaru Kokubo ,  Hideyuki Nagaishi ,  Nobuhisa Kobayashi

IPC分类号： H04W24/00

CPC分类号： H04W28/06 ,  H04L1/0002 ,  H04L1/0014 ,  H04L43/00 ,  H04L67/12 ,  H04L69/04 ,  H04L2001/0097 ,  H04W4/38 ,  H04W24/10 ,  H04W84/18 ,  Y02D70/00

摘要： A wireless communication device includes a sensor processing unit that generates sensor data including a measurement result acquired by a sensor; a communication measurement unit that generates communication quality data including a communication state for transmitting a packet; a compression determination unit that determines compression rates of first sensor data and first communication quality data according to the contents of the first sensor data including the transmitted sensor data and the generated sensor data or the contents of the first communication quality data including the transmitted sensor data and the generated communication quality data; a compression unit that compresses the first sensor data and the first communication quality data according to the determined compression rates; and a wireless communication unit that transmits a packet including the compressed first sensor data and the compressed first communication quality data to another wireless communication device or the access point.

摘要翻译： 无线通信装置包括传感器处理单元，其生成包括由传感器获取的测量结果的传感器数据; 通信测量单元，其生成包括用于发送分组的通信状态的通信质量数据; 压缩确定单元，其根据包括所发送的传感器数据和所生成的传感器数据的第一传感器数据的内容或包括所发送的传感器数据的第一通信质量数据的内容来确定第一传感器数据和第一通信质量数据的压缩率 和生成的通信质量数据; 压缩单元，其根据确定的压缩率压缩第一传感器数据和第一通信质量数据; 以及无线通信单元，其将包括压缩的第一传感器数据和压缩的第一通信质量数据的分组发送到另一无线通信设备或接入点。

公开(公告)号：US08179733B2

公开(公告)日：2012-05-15

申请号：US13080958

申请日：2011-04-06

申请人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

发明人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

IPC分类号： G11C7/00

CPC分类号： H03L7/107 ,  G11C5/025 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  H03L7/0814 ,  H03L7/0898 ,  H03L7/1072 ,  H03L2207/14

摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

摘要翻译： 一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间 的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域 形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。 电源通道也与其他数字电路无关地形成。

公开(公告)号：US07602665B2

公开(公告)日：2009-10-13

申请号：US12169253

申请日：2008-07-08

申请人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

发明人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

IPC分类号： G11C5/14

CPC分类号： H03L7/107 ,  G11C5/025 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  H03L7/0814 ,  H03L7/0898 ,  H03L7/1072 ,  H03L2207/14

摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.