公开(公告)号：US06483887B2

公开(公告)日：2002-11-19

申请号：US09992428

申请日：2001-11-26

申请人： Takashi Miyake ,  Kazuyuki Iwaguro

发明人： Takashi Miyake ,  Kazuyuki Iwaguro

IPC分类号： H01H4300

CPC分类号： H03K3/64 ,  G06F1/025 ,  H03K5/156

摘要： A timer control circuit includes timers that perform count operations. A signal selection circuit selectively passes underflow signals supplied from the timers, based on control signals. A flip-flop is supplied with an output of the signal selection circuit section as a toggle signal.

摘要翻译： 定时器控制电路包括执行计数操作的定时器。 信号选择电路基于控制信号选择性地通过从定时器提供的下溢信号。 触发器提供有信号选择电路部分的输出作为触发信号。

公开(公告)号：US06608508B1

公开(公告)日：2003-08-19

申请号：US10208768

申请日：2002-08-01

申请人： Kazuyuki Iwaguro ,  Shohei Maeda

发明人： Kazuyuki Iwaguro ,  Shohei Maeda

IPC分类号： H03L700

CPC分类号： H03K5/1534 ,  H03K2005/00247

摘要： A reset control apparatus, which carries out reset control in response to an external reset signal, includes a count start signal generating unit for producing a count start signal in response to the external reset signal, a counter for starting counting in response to the count start signal, and a reset signal generating unit for outputting an internal reset signal in response to the external reset signal, and for halting the output of the internal reset signal while the counter counts a predetermined count value. The reset control apparatus can solve a problem of a conventional reset control apparatus in that when the pulse width of the external reset signal passing through a noise canceler is narrower than the period of the clock signal, it cannot sample the signal, and hence cannot generate the internal reset signal.

摘要翻译： 根据外部复位信号执行复位控制的复位控制装置包括：计数开始信号生成单元，用于响应于外部复位信号产生计数开始信号;计数器，用于响应于计数开始开始计数 信号和复位信号产生单元，用于响应于外部复位信号输出内部复位信号，并且在计数器计数预定计数值时停止内部复位信号的输出。 复位控制装置可以解决传统的复位控制装置的问题，即当通过噪声消除器的外部复位信号的脉冲宽度比时钟信号的周期窄时，它不能对信号进行采样，因此不能产生 内部复位信号。

公开(公告)号：US06583748B1

公开(公告)日：2003-06-24

申请号：US10208822

申请日：2002-08-01

申请人： Kazuyuki Iwaguro ,  Mitsuru Sugita

发明人： Kazuyuki Iwaguro ,  Mitsuru Sugita

IPC分类号： H03M136

CPC分类号： H01L27/0266 ,  H03K17/08142 ,  H03K17/693

摘要： Analog input selection circuits comprising an input terminal, an output terminal, a transmission path extending between the input terminal and the output terminal, transmission switches that open or close the transmission path, an over-voltage protection switch which connects or does not connect the transmission path to the ground, a PMOS transistor provided between the input terminal and a power supply, and an NMOS transistor provided between the input terminal and the ground are formed on an identical semiconductor substrate. If the semiconductor substrate is P-type, then a region in which the NMOS transistor is formed is surrounded by an N-well region.

摘要翻译： 模拟输入选择电路，包括输入端子，输出端子，在输入端子和输出端子之间延伸的传输路径，打开或关闭传输路径的传输开关，连接或不连接传输的过电压保护开关 设置在输入端和电源之间的PMOS晶体管和设置在输入端和地之间的NMOS晶体管形成在同一半导体衬底上。 如果半导体衬底是P型，则其中形成NMOS晶体管的区域被N阱区域包围。

公开(公告)号：US5699285A

公开(公告)日：1997-12-16

申请号：US651545

申请日：1996-05-22

申请人： Atsushi Miyanishi ,  Kazuyuki Iwaguro

发明人： Atsushi Miyanishi ,  Kazuyuki Iwaguro

IPC分类号： G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F7/38

CPC分类号： G06F5/012

摘要： It is an object to realize in a floating point computation device a normalization circuit device which carries out normalization, unnormalization and 0 function operation at high speed. A circuit (3) outputs 1 from the most significant bit for the number obtained by adding 1 to a decimal number value of the exponent part input signal (A). AND operation of the signal (A") and the mantissa part input signal (B) and OR operation of all bits of the value ((3) provide a control signal (G'). A circuit (2) represents in a binary value (B') a number obtained by subtracting 1 from a number value of the bit position of the leading 1 from the most significant bit of the signal (B). A circuit (6) subtracts the valve (B') from the signal (A) and a circuit (7b) selects the signal (H) and a 0 value according to the signal (G') to obtain an exponent part output signal (C) after normalization. A circuit (5) retrieves the respective bit states of the signal B from the most significant bit to render "1" only the bit state of the position of the leading 1. A circuit (7a) selects the signal (B") and a decoded signal (A') according to the signal (G') to obtain a moved amount (D). A shifter (8) shifts the signal (B) according to the signal (D) to obtain a mantissa part output signal (E) after normalization.

摘要翻译： 在浮点计算装置中，实现高速进行归一化，非归一化和0功能操作的归一化电路装置。 电路（3）从通过将1加到指数部分输入信号（A）的十进制数值获得的数字的最高有效位输出1。 信号（A“）和尾数部分输入信号（B）的AND运算和值（（3））的所有位的”或“运算提供控制信号（G'），电路（2）以二进制 值（B'）通过从信号（B）的最高有效位从前导1的位位置的数值减去1得到的数字，电路（6）从信号（B'）中减去阀（B'） （A）和电路（7b）根据信号（G'）选择信号（H）和0值，以在归一化后获得指数部分输出信号（C），电路（5）检索各个位状态 信号B从最高有效位发送到“1”，仅使前导1的位置的位状态。电路（7a）根据（1）的选择信号（B“）和解码信号（A'）， 信号（G'）以获得移动量（D），移位器（8）根据信号（D）移位信号（B），以在归一化之后获得尾数部分输出信号（E）。