-
公开(公告)号：US07911369B2
公开(公告)日：2011-03-22
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译： 流水线式AD转换器（1）包括多个转换级（11,11 ...）。 在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。 数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。 充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2） 以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。 放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。
-
公开(公告)号：US20100149010A1
公开(公告)日：2010-06-17
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译： 流水线式AD转换器（1）包括多个转换级（11,11 ...）。 在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。 数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。 充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2） 以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。 放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。
-
公开(公告)号：US07808295B2
公开(公告)日：2010-10-05
申请号：US12296021
申请日：2007-06-15
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。 给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号 包括在该电平移位器中的晶体管（Mn1）是相位量X（0°
-
公开(公告)号：US20090134931A1
公开(公告)日：2009-05-28
申请号：US12296021
申请日：2007-06-15
IPC分类号： H03L5/00
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。 给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号 包括在该电平移位器中的晶体管（Mn1）是相位量X（0°
-
公开(公告)号：US07920002B2
公开(公告)日：2011-04-05
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K5/01
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。
-
公开(公告)号：US07633421B2
公开(公告)日：2009-12-15
申请号：US12093252
申请日：2007-07-30
申请人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
发明人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
IPC分类号： H03M1/12
CPC分类号： H03M1/123 , H03M1/1215 , H03M1/56
摘要： An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.
摘要翻译： A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。 每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。 具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12） 以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。
-
公开(公告)号：US20080315933A1
公开(公告)日：2008-12-25
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K3/00
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。
-
公开(公告)号：US08130608B2
公开(公告)日：2012-03-06
申请号：US12967498
申请日：2010-12-14
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译： 在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组 每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡 固定状态，然后将q个逆变器电路的输出从同相固定状态解除。
-
公开(公告)号：US20110080821A1
公开(公告)日：2011-04-07
申请号：US12967498
申请日：2010-12-14
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译： 在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组 每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡 固定状态，然后将q个逆变器电路的输出从同相固定状态解除。
-
公开(公告)号：US20090237281A1
公开(公告)日：2009-09-24
申请号：US12093252
申请日：2007-07-30
申请人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
发明人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
CPC分类号： H03M1/123 , H03M1/1215 , H03M1/56
摘要： An A/D converter includes: a plurality of A/D conversion circuits (10a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.
摘要翻译： A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。 每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。 具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12） 以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。
-
-
-
-
-
-
-
-
-
搜索结果
37 条记录 (耗时 0.02 秒)