公开(公告)号：US20070106428A1

公开(公告)日：2007-05-10

申请号：US11271460

申请日：2005-11-10

申请人： Takashi Omizo ,  Charles Johns ,  Michael Wang ,  Kazuaki Yazawa ,  Toshiyuki Hiroi

发明人： Takashi Omizo ,  Charles Johns ,  Michael Wang ,  Kazuaki Yazawa ,  Toshiyuki Hiroi

IPC分类号： G05D23/00

CPC分类号： G05D23/19

摘要： Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces temperatures associated with some of the functional blocks, but not others. One embodiment comprises an integrated circuit having multiple functional blocks (such as processor cores) and a set of thermal sensors coupled to sense the temperatures of the functional blocks. The integrated circuit includes control circuitry configured to receive signals from the thermal sensors, detect thermal events in the functional blocks and to individually adjust operation of the functional blocks to reduce the temperatures causing the thermal events. In one embodiment, the control circuitry includes a detection/control circuit coupled to each of the functional blocks and a thermal management unit configured to evaluate detected thermal events and to determine actions to be taken in response to the thermal events.

摘要翻译： 用于感测数字设备内的多个功能块的温度的系统和方法，并且以选择性地降低与一些功能块相关联的温度而不是其它功能块的方式来控制这些功能块的操作。 一个实施例包括具有多个功能块（例如处理器核）的集成电路和耦合以感测功能块的温度的一组热传感器。 集成电路包括控制电路，其被配置为从热传感器接收信号，检测功能块中的热事件并且单独地调整功能块的操作以降低导致热事件的温度。 在一个实施例中，控制电路包括耦合到每个功能块的检测/控制电路和被配置为评估检测到的热事件并且确定响应于热事件而采取的动作的热管理单元。

公开(公告)号：US07349762B2

公开(公告)日：2008-03-25

申请号：US11271460

申请日：2005-11-10

申请人： Takashi Omizo ,  Charles R. Johns ,  Michael F. Wang ,  Kazuaki Yazawa ,  Toshiyuki Hiroi

发明人： Takashi Omizo ,  Charles R. Johns ,  Michael F. Wang ,  Kazuaki Yazawa ,  Toshiyuki Hiroi

IPC分类号： G06F17/40

CPC分类号： G05D23/19

摘要： Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces temperatures associated with some of the functional blocks, but not others. One embodiment comprises an integrated circuit having multiple functional blocks (such as processor cores) and a set of thermal sensors coupled to sense the temperatures of the functional blocks. The integrated circuit includes control circuitry configured to receive signals from the thermal sensors, detect thermal events in the functional blocks and to individually adjust operation of the functional blocks to reduce the temperatures causing the thermal events. In one embodiment, the control circuitry includes a detection/control circuit coupled to each of the functional blocks and a thermal management unit configured to evaluate detected thermal events and to determine actions to be taken in response to the thermal events.

摘要翻译： 用于感测数字设备内的多个功能块的温度的系统和方法，并且以选择性地降低与一些功能块相关联的温度而不是其它功能块的方式来控制这些功能块的操作。 一个实施例包括具有多个功能块（例如处理器核）的集成电路和耦合以感测功能块的温度的一组热传感器。 集成电路包括控制电路，其被配置为从热传感器接收信号，检测功能块中的热事件并且单独地调整功能块的操作以降低导致热事件的温度。 在一个实施例中，控制电路包括耦合到每个功能块的检测/控制电路和被配置为评估检测到的热事件并且确定响应于热事件而采取的动作的热管理单元。

公开(公告)号：US07590774B2

公开(公告)日：2009-09-15

申请号：US11291735

申请日：2005-12-01

申请人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

发明人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

IPC分类号： G06F13/28 ,  G06F7/38 ,  G06F9/00

CPC分类号： G06F13/28

摘要： Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

摘要翻译： 公开了用于有效地切换处理元件之间的上下文的系统和方法。 这些系统和方法可以将处理元件的上下文传送到存储位置。 使用目标处理元件的DMA控制器，该存储位置的内容可以被传送到与目标处理元件相关联的另一存储位置。 然后，该上下文可以从该存储位置恢复到目标处理元件中的适当位置，并且目标处理元件然后可以利用该传送的上下文开始处理。

公开(公告)号：US20070162640A1

公开(公告)日：2007-07-12

申请号：US11291735

申请日：2005-12-01

申请人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

发明人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

摘要翻译： 公开了用于有效地切换处理元件之间的上下文的系统和方法。 这些系统和方法可将处理元件的上下文传送到存储位置。 使用目标处理元件的DMA控制器，该存储位置的内容可以被传送到与目标处理元件相关联的另一存储位置。 然后，该上下文可以从该存储位置恢复到目标处理元件中的适当位置，并且目标处理元件然后可以利用该传送的上下文开始处理。

公开(公告)号：US06260151B1

公开(公告)日：2001-07-10

申请号：US09038628

申请日：1998-03-12

申请人： Takashi Omizo ,  Yoshihiko Okazaki ,  Shigeki Muratake

发明人： Takashi Omizo ,  Yoshihiko Okazaki ,  Shigeki Muratake

IPC分类号： G06F1300

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172

摘要： In a computer system, a control signal line directly connecting a processor to a power sequence controller is provided and a PSC interface for exchanging a control signal with the power sequence controller is built in the processor. When all the devices connected to a specific IO bus have been out of use for a long time, the processor transmits a control signal to stop the supply of power to the IO bus to the power sequence controller. This stops power from being supplied to not only the devices connected to the IO bus but also the IO bus. As a result, the unnecessarily consumed power in the computer system is reduced remarkably.

摘要翻译： 在计算机系统中，提供将处理器直接连接到功率控制器的控制信号线，并且在处理器中内置有用于与控制信号交换控制信号的PSC接口。 当连接到特定IO总线的所有设备长时间不再使用时，处理器发送一个控制信号，以停止向该功率控制器向IO总线供电。 这不仅可以将电源不仅提供给连接到IO总线的设备，还可以提供给IO总线。 结果，计算机系统中不必要的消耗功率显着降低。

公开(公告)号：US5522058A

公开(公告)日：1996-05-28

申请号：US112811

申请日：1993-08-11

申请人： Shigeaki Iwasa ,  Takashi Omizo

发明人： Shigeaki Iwasa ,  Takashi Omizo

IPC分类号： G06F12/08

CPC分类号： G06F12/0813 ,  G06F12/0826 ,  G06F2212/2542 ,  G06F2212/622

摘要： A distributed shared-memory multiprocessor system capable of reducing a traffic on the shared bus, without imposing any constraint concerning the types of variables to be accessed in the parallel programs, such that a high system extensibility can be realized. The system is formed by a plurality of processor units coupled through a shared bus, where each processor unit comprises: a CPU; a main memory connected with the CPU through an internal bus, for storing a distributed part of data entries of a shared-memory of the system; a cache memory associated with the CPU and connected with the main memory through the internal bus, for caching selected data entries of the shared-memory; and a sharing management unit connected with the main memory and the cache memory through the internal bus, For interfacing the internal bus and the shared bus according to a sharing state for each data entry of the main memory and a cache state of each data entry of the cache memory.

摘要翻译： 一种分布式共享存储器多处理器系统，能够减少共享总线上的流量，而不会对并行程序中要访问的变量的类型施加任何约束，从而可以实现高系统可扩展性。 该系统由通过共享总线耦合的多个处理器单元形成，其中每个处理器单元包括：CPU; 通过内部总线与CPU连接的主存储器，用于存储系统的共享存储器的数据条目的分布式部分; 与CPU相关联的高速缓冲存储器，并通过内部总线与主存储器连接，用于缓存共享存储器的选定数据条目; 以及通过内部总线与主存储器和高速缓冲存储器连接的共享管理单元，用于根据主存储器的每个数据条目的共享状态和内部总线和共享总线的每个数据条目的高速缓存状态 缓存内存。

公开(公告)号：US08255614B2

公开(公告)日：2012-08-28

申请号：US12561924

申请日：2009-09-17

申请人： Takashi Omizo ,  Atsushi Kunimatsu

发明人： Takashi Omizo ,  Atsushi Kunimatsu

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/7201

摘要： An information processing device of an example of the invention comprises an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed, an order generation section that generates order information indicating a generation order of the writing operation, and a write control section that stores write information to the write address, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address.

摘要翻译： 本发明实施例的信息处理装置包括：地址生成部，其生成表示非易失性存储器中的写入位置的写入地址，使得写入位置被移位，以便抑制每个位置的重叠写入次数 执行从处理器对非易失性存储器的写入操作时的非易失性存储器，产生指示写入操作的生成顺序的顺序信息的顺序生成部，以及将写入信息存储到写入地址的写入控制部， 将订单信息提供给非易失性存储器，使得订单信息与所存储的写入信息和写入地址中的至少一个相关。

公开(公告)号：US20100185804A1

公开(公告)日：2010-07-22

申请号：US12561924

申请日：2009-09-17

申请人： Takashi Omizo ,  Atsushi Kunimatsu

发明人： Takashi Omizo ,  Atsushi Kunimatsu

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/7201

摘要： An information processing device of an example of the invention comprises an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed, an order generation section that generates order information indicating a generation order of the writing operation, and a write control section that stores write information to the write address, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address.

摘要翻译： 本发明实施例的信息处理装置包括：地址生成部，其生成表示非易失性存储器中的写入位置的写入地址，使得写入位置被移位，以便抑制每个位置的重叠写入次数 执行从处理器对非易失性存储器的写入操作时的非易失性存储器，产生指示写入操作的生成顺序的顺序信息的顺序生成部，以及将写入信息存储到写入地址的写入控制部， 将订单信息提供给非易失性存储器，使得订单信息与所存储的写入信息和写入地址中的至少一个相关。

公开(公告)号：US06820119B1

公开(公告)日：2004-11-16

申请号：US09659680

申请日：2000-09-11

申请人： Takashi Omizo

发明人： Takashi Omizo

IPC分类号： G06F15173

CPC分类号： G08C23/04 ,  H04L63/10

摘要： A computer system capable of system management from a terminal having a wireless communication function is provided with an IrDA-IF having an IrDA port capable of infrared wireless communication between the terminal and the computer system itself and a system management controller connected to the IrDA-IF, the system management controller performing the system management instructed by the terminal through infrared wireless communication with the terminal through the IrDA-IF.

摘要翻译： 具有能够从具有无线通信功能的终端进行系统管理的计算机系统设置有具有能够在终端和计算机系统本身之间进行红外无线通信的IrDA端口的IrDA-IF和连接到IrDA-IF的系统管理控制器 ，所述系统管理控制器通过所述终端通过与所述终端通过IrDA-IF进行红外无线通信来执行由所述终端指示的系统管理。