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公开(公告)号：US07446369B2
公开(公告)日：2008-11-04
申请号：US11196434
申请日：2005-08-04
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4232 , H01L29/513
摘要： A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.
摘要翻译： 半导体存储器件可以包括介于浮置栅极和控制栅极之间的高K电介质材料的隔间电介质层。 使用这种隔间高K电介质就可以使用Fowler-Nordheim隧道擦除存储器件。
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公开(公告)号：US07202128B1
公开(公告)日：2007-04-10
申请号：US11165330
申请日：2005-06-24
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/66833 , Y10S438/954
摘要： A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor is formed to include thin gate oxide via a dry oxidation technique and a gate layer on the thin gate oxide. The thin gate oxide is formed without subjecting the thin gate oxide to thermal annealing with N2O.
摘要翻译： 形成存储器件的方法包括在衬底上形成存储器堆叠。 存储器堆叠包括用作隔间电介质层的氧化铝层。 在与存储器堆叠分离的区域中的衬底上形成晶体管。 晶体管通过干式氧化技术和薄栅极氧化物上的栅极层形成为包括薄栅极氧化物。 形成薄栅氧化层，而不需要使薄栅氧化层与N 2 O 2进行热退火。
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公开(公告)号：US07919809B2
公开(公告)日：2011-04-05
申请号：US12170327
申请日：2008-07-09
申请人： Dana Lee , Henry Chin , James K. Kai , Takashi Whitney Orimoto , Vinod R. Purayath , George Matamis
发明人： Dana Lee , Henry Chin , James K. Kai , Takashi Whitney Orimoto , Vinod R. Purayath , George Matamis
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L21/84 , H01L27/1203
摘要： A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.
摘要翻译： 公开了一种包括一组非易失性存储元件的存储器系统。 给定的存储单元在浮动栅极上方具有电介质盖。 在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。 电介质盖减少了浮动栅极和控制栅极之间的漏电流。 电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。
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公开(公告)号：US07294547B1
公开(公告)日：2007-11-13
申请号：US11128392
申请日：2005-05-13
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/513
摘要： A semiconductor memory device may include an intergate dielectric layer of high-K dielectric materials interposed between a charge storing layer and a control gate. The high-K materials may be deposited in such a manner that the materials are gradually graded with respect to one another.
摘要翻译： 半导体存储器件可以包括介于电荷存储层和控制栅极之间的高K电介质材料的隔间电介质层。 高K材料可以以使得材料相对于彼此逐渐分级的方式沉积。
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公开(公告)号：US08946803B2
公开(公告)日：2015-02-03
申请号：US11951998
申请日：2007-12-06
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L27/108 , H01L29/423
CPC分类号： H01L21/28273 , H01L27/10844 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.
摘要翻译： 浮动栅极存储器阵列的浮动栅极在位线方向和字线方向都具有倒T形。 使用分离形成浮动栅极的两个多晶硅层的蚀刻停止层形成浮动栅极。 字线在一个示例中在浮动栅极上延伸，并且在另一示例中，字线在浮动栅极之间延伸。
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公开(公告)号：US08278203B2
公开(公告)日：2012-10-02
申请号：US12845329
申请日：2010-07-28
IPC分类号： H01L21/44
CPC分类号： H01L27/11524 , H01L29/42376 , H01L29/66545
摘要： Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.
摘要翻译： 公开了在非易失性存储器中制造控制栅极的方法。 当形成用于浮动栅极存储器单元和晶体管控制栅极的堆叠时，可以在堆叠的顶部形成牺牲材料。 在堆叠之间形成绝缘之后，可以去除牺牲材料以露出开口。 在一些实施例中，在要形成晶体管的控制栅极的区域中形成切口。 然后在开口中形成金属，其可以包括切口区域。 因此，具有至少部分金属控制栅极和至少部分金属控制栅极的晶体管的浮动栅极存储单元可以在相同的工艺中形成。 可以在沉积金属之前形成阻挡层，以防止多晶硅在控制栅中的硅化。
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公开(公告)号：US20120025289A1
公开(公告)日：2012-02-02
申请号：US12845329
申请日：2010-07-28
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11524 , H01L29/42376 , H01L29/66545
摘要： Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.
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公开(公告)号：US20120187468A1
公开(公告)日：2012-07-26
申请号：US13439260
申请日：2012-04-04
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L27/11524 , H01L29/42376 , H01L29/66545
摘要： Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.
摘要翻译： 公开了在非易失性存储器中制造控制栅极的方法。 当形成用于浮动栅极存储器单元和晶体管控制栅极的堆叠时，可以在堆叠的顶部形成牺牲材料。 在堆叠之间形成绝缘之后，可以去除牺牲材料以露出开口。 在一些实施例中，在要形成晶体管的控制栅极的区域中形成切口。 然后在开口中形成金属，其可以包括切口区域。 因此，具有至少部分金属控制栅极和至少部分金属控制栅极的晶体管的浮动栅极存储单元可以在相同的工艺中形成。 可以在沉积金属之前形成阻挡层，以防止多晶硅在控制栅中的硅化。
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9.发明授权公开(公告)号：US08546214B2
公开(公告)日：2013-10-01
申请号：US12887328
申请日：2010-09-21
申请人： Takashi Whitney Orimoto , Atsushi Suyama , Ming Tian , Henry Chin , Henry Chien , Vinod Robert Purayath , Dana Lee
发明人： Takashi Whitney Orimoto , Atsushi Suyama , Ming Tian , Henry Chin , Henry Chien , Vinod Robert Purayath , Dana Lee
IPC分类号： H01L21/8242
CPC分类号： H01L21/28291 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/788
摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.
摘要翻译： 公开了非电压存储和用于制造非易失性存储器的技术。 在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。 在一个实施例中，控制栅极的下部是p型多晶硅。 控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。 因此，如果控制门耗尽，可能会发生的一些问题得到缓解。 例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。
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公开(公告)号：US08409951B2
公开(公告)日：2013-04-02
申请号：US13439260
申请日：2012-04-04
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L29/42376 , H01L29/66545
摘要： Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.
摘要翻译： 公开了在非易失性存储器中制造控制栅极的方法。 当形成用于浮动栅极存储器单元和晶体管控制栅极的堆叠时，可以在堆叠的顶部形成牺牲材料。 在堆叠之间形成绝缘之后，可以去除牺牲材料以露出开口。 在一些实施例中，在要形成晶体管的控制栅极的区域中形成切口。 然后在开口中形成金属，其可以包括切口区域。 因此，具有至少部分金属控制栅极和至少部分金属控制栅极的晶体管的浮动栅极存储单元可以在相同的工艺中形成。 可以在沉积金属之前形成阻挡层，以防止多晶硅在控制栅中的硅化。
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