公开(公告)号：US09106256B2

公开(公告)日：2015-08-11

申请号：US13818709

申请日：2011-08-25

申请人： Yuji Shinohara ,  Atsushi Kikuchi ,  Makiko Yamamoto ,  Takashi Yokokawa

发明人： Yuji Shinohara ,  Atsushi Kikuchi ,  Makiko Yamamoto ,  Takashi Yokokawa

IPC分类号： H03M13/00 ,  H03M13/05 ,  H03M13/03 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/35 ,  H04L27/36 ,  H03M13/15

CPC分类号： H03M13/05 ,  H03M13/036 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2906 ,  H03M13/356 ,  H03M13/6552 ,  H04L27/36

摘要： A data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder performs encoding using an LDPC code having a code length of 4320 bits and a coded rate of one of four types including ½, 7/12, ⅔, ¾. A parity check matrix H of the LDPC code is configured by arranging elements of 1's of an information matrix, which are determined based on a parity check matrix initial value table of the parity check matrix H representing positions of elements of 1's of the information matrix corresponding to an information length according to the code length and the coded rate for every 72 columns, in a column direction at a period of 72 columns. The parity check matrix initial value table, for example, is used for digital broadcasting for mobile terminals.

摘要翻译： 一种数据处理装置和数据处理方法，能够提高数据的误差抵抗能力。 LDPC编码器使用码长为4320位的LDPC码和包括½，7/12，⅔，¾的四种类型之一的编码速率来执行编码。 通过布置基于奇偶校验矩阵H的奇偶校验矩阵初始值表确定的信息矩阵的1的元素来表示LDPC码的奇偶校验矩阵H，该奇偶校验矩阵初始值表示对应于信息矩阵的1的元素的位置 根据每72列的码长和编码速率在72列的列方向上的信息长度。 奇偶校验矩阵初始值表例如用于移动终端的数字广播。

公开(公告)号：US09094043B2

公开(公告)日：2015-07-28

申请号：US13982494

申请日：2012-02-01

申请人： Yuji Shinohara ,  Makiko Yamamoto ,  Takashi Yokokawa

发明人： Yuji Shinohara ,  Makiko Yamamoto ,  Takashi Yokokawa

IPC分类号： H03M13/00 ,  H03M13/09 ,  H03M13/03 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H03M13/15 ,  H04L27/26

CPC分类号： H03M13/09 ,  H03M13/036 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2906 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0065 ,  H04L1/0072 ,  H04L27/2626 ,  H04L27/2647

摘要： A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code.

摘要翻译： 一种数据处理装置和能够改善抵抗误差的数据处理方法。 具有16200比特的码长N的LDPC码的码比特被写入例如八个存储单元。 当代码位被存储在存储单元中时，执行改变每个存储单元的代码位的存储开始位置的处理，作为对LDPC码的比特进行排序的排序处理，使得与 LDPC码的奇偶校验矩阵的任意行中的1个不包含在从存储单元读取的单个符号中。 本技术可以应用于例如LDPC码的传输。

公开(公告)号：US20100325512A1

公开(公告)日：2010-12-23

申请号：US12743454

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto

发明人： Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： H03M13/27 ,  G06F11/10

CPC分类号： H03M13/1165 ,  H03M13/1137 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/27 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3416 ,  H04L27/3488 ,  H04L2001/0093

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of code bits of an LDPC code such as burst errors or erasure.Where one symbol is formed from two or more code bits of an LDPC (Low Density Parity Check) code, a column twist interleaver 24 carries out a re-arrangement process of re-arranging the code bits of the LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not mapped to one symbol. The present invention can be applied, for example, to a transmission apparatus which transmits an LDPC code.

摘要翻译： 本发明涉及一种数据处理装置和数据处理方法，其可以提高诸如突发错误或擦除之类的LDPC码的码位的容错。 在一个符号由LDPC（低密度奇偶校验）码的两个或多个码位形成的情况下，列扭曲交织器24执行重新排列LDPC码的码位的重新布置处理，使得多个 对应于包括在奇偶校验矩阵的一个任意行中的值1的码位不映射到一个符号。 本发明可以应用于例如发送LDPC码的发送装置。

公开(公告)号：US20100299572A1

公开(公告)日：2010-11-25

申请号：US12743649

申请日：2008-11-18

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H04L27/3416 ,  H03M13/036 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/271 ,  H03M13/356 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3488 ,  H04L27/36

摘要： A data processing apparatus, a data processing method, an encoding apparatus and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve the tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of ⅔, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by bi and yi, respectively, replacement of allocating b0 to y15, b1 to y7, b2 to y1, b3 to y5, b4 to y6, b5 to y13, b6 to y11, b7 to y9, b8 to y8, b9 to y14, b10 to y12, b11 to y3, b12 to y0, b13 to y10, b14 to y4 and b15 to y2.

摘要翻译： 可以应用于例如用于发送LDPC码等的传输系统的数据处理装置，数据处理方法，编码装置和编码方法，并且可以提高对误差的容限。 在DVB-S.2中规定的并且具有64,800的码长和an的编码率的LDPC码中，替换mb个码比特，并且替换后的码比特成为b符号的符号比特。 当m为8且b为2时，分别用b 1和y i表示从8×2码位的最高有效位和2个连续符号的8×2符号位的第i + 1位，将b0分配给 y15，b1〜y7，b2〜y1，b3〜y5，b4〜y6，b5〜y13，b6〜y11，b7〜y9，b8〜y8，b9〜y14，b10〜y12，b11〜y3，b12〜y0， b13〜y10，b14〜y4，b15〜y2。

公开(公告)号：US20100275101A1

公开(公告)日：2010-10-28

申请号：US12744400

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1165 ,  H03M13/036 ,  H03M13/255 ,  H03M13/2703 ,  H03M13/271 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3416 ,  H04L27/3488

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。 根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组 以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。

公开(公告)号：US20090217122A1

公开(公告)日：2009-08-27

申请号：US11912485

申请日：2005-04-25

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Misa Nakane

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Misa Nakane

IPC分类号： H03M13/19 ,  G06F17/10 ,  G06F17/16 ,  G06F11/10

CPC分类号： H03M13/1168 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/1185 ,  H03M13/6502 ,  H03M13/6516 ,  H03M13/6561

摘要： The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adder 13 integrates the product of an information word D13 of six bits supplied from a cyclic shift circuit 12 and the information part of a check matrix H corresponding to the information for each row in a unit of six rows and supplies the integrated value as a sum D15 to a RAM 14. The RAM 14 stores the sum D15. Further, the RAM 14 successively reads out sums D16 of 2 bits stored already therein and supplies the read out sums D16 as sums D17 to an accumulator 16 through an interleaver 15. The accumulator 16 integrates the sums D17 and outputs a sum D18 obtained as a result of the integration as a parity bit p of a codeword c through a selector 17. The present invention can be applied to an apparatus of a broadcasting station which transmits a satellite broadcast.

摘要翻译： 本发明涉及一种可以在不改变线性码的编码中的操作速度的情况下减小电路规模的编码装置和编码方法。 加法器13将从循环移位电路12提供的六位的信息字D13和对应于每行的信息的检查矩阵H的信息部分的乘积以六行的单位积分，并将积分值作为 总和D15到RAM14.RAM14存储总和D15。 此外，RAM14连续地读出其中已经存储的2位的和D16，并通过交织器15将累加器D16作为和D17提供给累加器16.累加器16对和D17进行积分，并输出作为 作为通过选择器17的码字c的奇偶校验位p的积分的结果。本发明可以应用于发送卫星广播的广播站的装置。

公开(公告)号：US20090158128A1

公开(公告)日：2009-06-18

申请号：US12335834

申请日：2008-12-16

申请人： Takashi Yokokawa ,  Makiko Yamamoto

发明人： Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： H03M13/05 ,  G06F11/07

CPC分类号： H03M13/45 ,  H03M13/15 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/37

摘要： A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media.

摘要翻译： 一种用于环R上的线性码的解码装置，所述解码装置包括：多个存储介质; 和处理部; 其中所述处理部分在先前时间使用所有符号的可靠性的一部分来更新迭代解码过程中的每个符号的可靠性，以增加每个符号的可靠性，并且还保留用于更新保留的可靠性信息的部分和部分 未用于在两个单独的存储介质上更新保留的可靠性信息。

公开(公告)号：US08578237B2

公开(公告)日：2013-11-05

申请号：US12744400

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/036 ,  H03M13/255 ,  H03M13/2703 ,  H03M13/271 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3416 ,  H04L27/3488

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。 根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组 以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。

公开(公告)号：US08499214B2

公开(公告)日：2013-07-30

申请号：US12743398

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

IPC分类号： H03M13/00

CPC分类号： H04L27/2647 ,  H03M13/033 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/2906 ,  H03M13/356 ,  H03M13/6552 ,  H03M13/6555

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器25根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中替换mb比特，并将替换后的码比特设置为b符号的符号比特。 例如，当m为12且b为1时，其中来自12×1码位的最高有效位的第i + 1位和一个符号的12×1符号位表示为位bi和yi，替换为 分配例如b0至y8，b1至y0，b2至y6，b3至y1，b4至y4，b5至y5，b6至y2，b7至y3，b8至y7，b9至y10，b10至y11和b11 到y9进行。 本发明可以应用于例如用于发送LDPC码等的传输系统。

公开(公告)号：US08312353B2

公开(公告)日：2012-11-13

申请号：US12335834

申请日：2008-12-16

申请人： Takashi Yokokawa ,  Makiko Yamamoto

发明人： Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： H03M13/00

CPC分类号： H03M13/45 ,  H03M13/15 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/37

摘要： A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media.

摘要翻译： 一种用于环R上的线性码的解码装置，所述解码装置包括：多个存储介质; 和处理部; 其中所述处理部分在先前时间使用所有符号的可靠性的一部分来更新迭代解码过程中的每个符号的可靠性，以增加每个符号的可靠性，并且还保留用于更新保留的可靠性信息的部分和部分 未用于在两个单独的存储介质上更新保留的可靠性信息。