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    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5038191A

    公开(公告)日：1991-08-06

    申请号：US486842

    申请日：1990-03-01

    申请人： Takehiro Hasegawa ,  Koji Sakui ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Koji Sakui ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    IPC分类号： G11C11/41 ,  G11C11/401 ,  G11C11/404 ,  G11C11/411 ,  G11C11/412 ,  H01L21/331 ,  H01L21/8229 ,  H01L27/102 ,  H01L29/73 ,  H01L29/732

    CPC分类号： G11C11/4113 ,  G11C11/404 ,  G11C11/412

    摘要： A semiconductor memory device comprises a memory array including a plurality of memory cells arranged in a matrix form, a plurality of word lines arranged in column and a plurality of bit lines arranged in row. Each memory cell includes a bipolar transistor in which a collector-emitter voltage is controlled so that the polarity of a base current changes is changed in accordance with an increase in a base-emitter voltage, and a switching element, provided between the base of the bipolar transistor and an associated bit line and controllable by an associated word line. A switch circuit is provided for applying a collector voltage to the collector of the bipolar transistor smaller in a second state where an associated one of the memory cells is holding data than in a second state where the associated memory cell is accessible for data reading and data writing.

    摘要翻译： 半导体存储器件包括存储器阵列，其包括以矩阵形式布置的多个存储器单元，排列成列的多个字线和排成行的多个位线。 每个存储单元包括双极晶体管，其中控制集电极 - 发射极电压，使得基极电流变化的极性根据基极 - 发射极电压的增加而改变，并且开关元件设置在基极 双极晶体管和相关联的位线，并且可由相关联的字线控制。 提供一种开关电路，用于在第二状态下将集电极电压施加到双极晶体管的集电极，在第二状态下，相关联的一个存储单元保持数据而不是相关联的存储单元可访问用于数据读取和数据的第二状态 写作。

    Dynamic random access memory device
    5.
    发明授权
    Dynamic random access memory device 失效
    动态随机存取存储器

    公开(公告)号：US06295241B1

    公开(公告)日：2001-09-25

    申请号：US08251649

    申请日：1994-05-31

    申请人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

    发明人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

    IPC分类号： G11C702

    CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/14 ,  G11C11/4099

    摘要： Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

    摘要翻译： 这里公开了具有高集成度密度的动态半导体存储器，其具有在基板上形成的并行字线和并行位线。 位线包括一对位线。 存储器单元耦合到字线和位线对的一个位线。 存储单元由亚微米尺寸的MOSFET组成。 读出放大器部分连接到一对位线，并且在数据读出模式下感测和放大一对位线之间的电位差。 放大器部分具有BIMOS结构，具有MOSFET和双极晶体管。 它具有由双极晶体管组成的驱动器部分。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5517457A

    公开(公告)日：1996-05-14

    申请号：US360289

    申请日：1994-12-21

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5615163A

    公开(公告)日：1997-03-25

    申请号：US598706

    申请日：1996-02-08

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Semiconductor memory device having a plurality of transfer gates and improved word line and column select timing for high speed write operations
    8.
    发明授权
    Semiconductor memory device having a plurality of transfer gates and improved word line and column select timing for high speed write operations 失效
    具有多个传输门的半导体存储器件和用于高速写入操作的改进的字线和列选择定时

    公开(公告)号：US06198687B1

    公开(公告)日：2001-03-06

    申请号：US08716884

    申请日：1996-09-20

    申请人： Koji Sakui ,  Kazunori Ohuchi ,  Fujio Masuoka

    发明人： Koji Sakui ,  Kazunori Ohuchi ,  Fujio Masuoka

    IPC分类号： G11C11407

    CPC分类号： G11C8/18

    摘要： A semiconductor memory device which receives a row address strobe (RAS) signal and a column address strobe (CAS) signal from an external device. The device includes rewritable memory cells formed on a semiconductor substrate, a plurality of bit lines, a plurality of word lines, and a transfer gate coupled between the bit lines and input/output (I/O) lines and controlled by a column select line or signal. In one embodiment, a first transfer gate is connected between the bit lines and a second transfer gate, the second transfer gate connected between the first transfer gate and an input/output (I/O) line and controlled by a column select line (CSL). A third transfer gate may also by provided. The first transfer gate is driven in response to a clock signal which is enabled at substantially the same time as a word line of the plurality of word lines is selected during both read and write cycles. Thus, during a write cycle in which the CAS signal is enabled prior to the RAS signal, a selected CSL can be increased from a first voltage (VSS) to one of a second voltage (Vdd) and {fraction (3/2)} Vdd as soon as a column address is input.

    摘要翻译： 从外部设备接收行地址选通（RAS）信号和列地址选通（CAS）信号的半导体存储器件。 该器件包括形成在半导体衬底上的可重写存储单元，多个位线，多个字线和耦合在位线和输入/输出（I / O）线之间并由列选择线控制的传输栅极 或信号。 在一个实施例中，第一传输门连接在位线和第二传输门之间，第二传输门连接在第一传输门和输入/输出（I / O）线之间，并由列选择线（CSL ）。 也可以通过提供第三传输门。 响应于在读取和写入周期期间选择多个字线的字线的基本上相同的时间使能的时钟信号来驱动第一传输门。 因此，在RAS信号之前的CAS信号被使能的写周期中，所选择的CSL可以从第一电压（VSS）增加到第二电压（Vdd）和{分数（3/2）}之一 一旦列地址被输入，就会Vdd。

    Semiconductor memory using dynamic ram cells
    9.
    发明授权
    Semiconductor memory using dynamic ram cells 失效
    半导体存储器使用动态RAM单元

    公开(公告)号：US4943944A

    公开(公告)日：1990-07-24

    申请号：US275501

    申请日：1988-11-23

    申请人： Koji Sakui ,  Tsuneaki Fuse ,  Fujio Masuoka

    发明人： Koji Sakui ,  Tsuneaki Fuse ,  Fujio Masuoka

    IPC分类号： G11C7/10 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

    CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/1051

    摘要： Bit-line pairs and word lines are disposed perpendicular to one another and dRAM cells are placed at their intersections. A dummy cell is connected to each of the bit-line pairs. A bit-line sense amplifier and an equalizer are connected to one end of the bit-line pair. The other end of the bit-line pair is connected to a latch type memory cell via a first transfer gate. The latch type memory cell are further connected to input/output line pair via a second transfer gate controlled by a column select line. During a RAS active period in a read cycle a word line is selected so that data is read from a dRAM cell and the dummy cell connected to the selected word line onto the bit-line pairs. The bit-line sense amplifiers are activated so that the levels of the bit lines become determinate. The first transfer gates are subsequently turned on to transfer the data on the bit-line pairs to the latch type cells. After the memory cells are rewritten into, the selected word line is reset and the latch type memory cells are electrically disconnected from the bit-line pairs. The equalizers operate to precharge the bit-line pairs. When CAS is rendered active and a column is selected, a corresponging second transfer gate is turned on so that data in the latch type memory cell is read out onto the input/output line pairs.

    摘要翻译： 位线对和字线彼此垂直设置，并且dRAM单元被放置在它们的相交处。 虚拟单元连接到每个位线对。 位线读出放大器和均衡器连接到位线对的一端。 位线对的另一端通过第一传输门连接到锁存型存储单元。 闩锁型存储单元还经由由列选择线控制的第二传输门连接到输入/输出线对。 在读周期的RAS活动期间，选择字线，使得从dRAM单元读取数据，将连接到选定字线的虚拟单元读取到位线对上。 位线读出放大器被激活，使得位线的电平变得确定。 随后接通第一传输门，将位线对上的数据传送到锁存型单元。 在重写存储器单元之后，所选择的字线被复位，闩锁型存储单元与位线对电连接。 均衡器用于对位线对进行预充电。 当CAS被激活并选择列时，相应的第二传输门被导通，使得锁存型存储单元中的数据被读出到输入/输出线对上。

    Semiconductor memory device including circuitry for activating and deactivating a word line within a single RAS cycle
    10.
    发明授权
    Semiconductor memory device including circuitry for activating and deactivating a word line within a single RAS cycle 失效
    半导体存储器件包括用于在单个RAS周期内激活和去激活字线的电路

    公开(公告)号：US5596543A

    公开(公告)日：1997-01-21

    申请号：US969363

    申请日：1992-10-30

    申请人： Koji Sakui ,  Kazunori Ohuchi ,  Fujio Masuoka

    发明人： Koji Sakui ,  Kazunori Ohuchi ,  Fujio Masuoka

    IPC分类号： G11C8/18 ,  G11C11/407

    CPC分类号： G11C8/18

    摘要： A semiconductor memory device includes random-access memory cells arranged as an integrated memory cell array, a plurality of bit lines for exchanging data with each of the memory cells, and a plurality of word lines intersecting with the bit lines. An accessing method is applied to an address multiplexed type device in which a column address for selecting a bit line and a row address for selecting a word line are obtained from a single circuit. In this device, the input order of the column and row addresses during a read cycle differs from that during a write cycle. One of the word lines of the device is made active and then inactive during an active period of a row address strobe signal thereby speeding up the read/write operation.

    摘要翻译： 半导体存储器件包括布置为集成存储单元阵列的随机存取单元阵列，用于与每个存储单元交换数据的多个位线以及与位线相交的多个字线。 一种访问方法被应用于地址复用型设备，其中从单个电路获得用于选择位线的列地址和用于选择字线的行地址。 在该器件中，读周期中列和行地址的输入顺序与写周期中的不同。 在行地址选通信号的有效期间，器件的字线之一被激活，然后不活动，从而加速读/写操作。