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    Test apparatus and test method
    3.
    发明申请
    Test apparatus and test method 失效
    试验装置及试验方法

    公开(公告)号：US20070022346A1

    公开(公告)日：2007-01-25

    申请号：US11495186

    申请日：2006-07-28

    Applicant: Hiroaki Nishimine ,  Hirokatsu Niijima ,  Takeo Miura

    Inventor： Hiroaki Nishimine ,  Hirokatsu Niijima ,  Takeo Miura

    IPC: G01R31/28

    CPC classification number: G01R31/31932 ,  G01R31/31924

    Abstract: A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal with a predetermined reference voltage and a setting voltage output section 110 for setting the voltage of the test signal to a predetermined voltage value to cause the driver 122 to terminate the transmission path of the result signal when the test apparatus reads from the device under test 15.

    Abstract translation: 提供了一种用于测试被测设备15的测试装置。 测试装置包括用于将测试信号施加到被测器件的驱动器122，用于将由被测器件15输出的结果信号与所施加的测试信号相对应的比较器128与预定参考电压进行比较;以及设定电压输出部分 110，用于将测试信号的电压设置为预定电压值，以使得当测试设备从被测器件15读取时，驱动器122终止结果信号的传输路径。

    Test apparatus and test method
    4.
    发明授权
    Test apparatus and test method 失效
    试验装置及试验方法

    公开(公告)号：US07409615B2

    公开(公告)日：2008-08-05

    申请号：US11495186

    申请日：2006-07-28

    Applicant: Hiroaki Nishimine ,  Hirokatsu Niijima ,  Takeo Miura

    Inventor： Hiroaki Nishimine ,  Hirokatsu Niijima ,  Takeo Miura

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: G01R31/31932 ,  G01R31/31924

    Abstract: A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal with a predetermined reference voltage and a setting voltage output section 110 for setting the voltage of the test signal to a predetermined voltage value to cause the driver 122 to terminate the transmission path of the result signal when the test apparatus reads from the device under test 15.

    Abstract translation: 提供了一种用于测试被测设备15的测试装置。 测试装置包括用于将测试信号施加到被测器件的驱动器122，用于将由被测器件15输出的结果信号与所施加的测试信号相对应的比较器128与预定参考电压进行比较;以及设定电压输出部分 110，用于将测试信号的电压设置为预定电压值，以使得当测试设备从被测器件15读取时，驱动器122终止结果信号的传输路径。

    Method and apparatus for testing semiconductor devices
    5.
    发明授权
    Method and apparatus for testing semiconductor devices 有权
    用于半导体器件测试的方法和装置

    公开(公告)号：US06789224B2

    公开(公告)日：2004-09-07

    申请号：US09761199

    申请日：2001-01-16

    Applicant: Takeo Miura

    Inventor： Takeo Miura

    IPC: G01R3128

    CPC classification number: G01R31/31937

    Abstract: Data output from a semiconductor device under test and a reference clock output therefrom in synchronization with the data are sampled by slightly phased-apart multiphase strobe pulses. The phases of points of change of the output data and the reference clock are obtained from the sampled outputs, then the phase difference between them is measured, and a check is made to determine if the phase difference falls within a predetermined range, thereby evaluating the semiconductor device under test on a pass/fail basis.

    Abstract translation: 从被测半导体器件输出的数据和与数据同步输出的参考时钟通过稍微相位分开的多相选通脉冲进行采样。 从采样输出获得输出数据和参考时钟的变化点的相位，然后测量它们之间的相位差，并进行检查以确定相位差是否在预定范围内，由此评估 半导体器件在通过/失败的基础上进行测试。

    Apparatus and method for testing semiconductor device
    6.
    发明授权
    Apparatus and method for testing semiconductor device 有权
    半导体器件测试装置及方法

    公开(公告)号：US07283920B2

    公开(公告)日：2007-10-16

    申请号：US10732763

    申请日：2003-12-10

    Applicant: Masaru Doi ,  Takeo Miura

    Inventor： Masaru Doi ,  Takeo Miura

    IPC: G01M19/00

    CPC classification number: G01R31/31725 ,  G01R31/02 ,  G01R31/31937

    Abstract: A phase difference between a timing of rising or falling of the data read from a semiconductor device to be test and a timing of rising or falling of a reference clock outputted synchronized with the data is measured by operating sampling with strobe pulses configured with multi-phase pulses given the phase difference by a small amount in regard to the timing of the data and the timing of the reference clock. In addition, a glitch of the data is detected, and the quality of the semiconductor device to be tested is judged based on the phase difference and/or the glitch.

    Abstract translation: 从被测半导体器件读出的数据的上升或下降定时与数据同步输出的基准时钟的上升或下降时间之间的相位差通过以多相配置的选通脉冲进行采样来测量 相对于数据的定时和参考时钟的定时，给予相位差少的脉冲。 此外，检测数据的毛刺，并且基于相位差和/或毛刺来判断要测试的半导体器件的质量。

    Temperature balanced circuit
    7.
    发明授权
    Temperature balanced circuit 失效
    温度平衡电路

    公开(公告)号：US5818277A

    公开(公告)日：1998-10-06

    申请号：US790228

    申请日：1997-01-28

    Applicant: Takeo Miura

    Inventor： Takeo Miura

    IPC: H03K5/135 ,  H03H11/26

    CPC classification number: H03K5/135

    Abstract: A temperature balanced circuit is provided which is capable of, in case a CMOS.cndot.IC is utilized as a delay circuit, giving a constant delay time to an input signal to the delay circuit even if the frequency of the input signal is varied. A delay circuit 11 and a dummy circuit 11 having the same construction as that of the delay circuit are provided in a CMOS.cndot.IC. There are provided a counter counting first pulse signals CP1 supplied to the delay circuit during a fixed time interval and arithmetic unit finding a difference between a count value of this counter and a predetermined value, and the same number of second pulse signals as the difference value found by the arithmetic unit is supplied to the dummy circuit, thereby to define to a constant value both the number of the first pulses and the number of the second pulses supplied to the CMOS.cndot.IC within a unit time interval, which results in uniformity of an amount of heat generated in the CMOS.cndot.IC.

    Abstract translation: 提供了一种温度平衡电路，其能够在将CMOS.IC用作延迟电路的情况下，即使改变输入信号的频率，给延迟电路的输入信号提供恒定的延迟时间。 具有与延迟电路相同结构的延迟电路11和虚拟电路11设置在CMOS.IC中。 提供了在固定时间间隔内提供给延迟电路的第一脉冲信号CP1的计数器，并且计算单元找到该计数器的计数值与预定值之间的差异以及相同数量的第二脉冲信号作为差值 由运算单元发现的虚拟电路被提供给虚拟电路，从而将单位时间间隔内的第一脉冲的数量和提供给CMOS.IC的第二脉冲的数量定义为恒定值，这导致均匀性 在CMOS.IC中产生的热量。

    Semiconductor device testing apparatus
    8.
    发明授权
    Semiconductor device testing apparatus 失效
    半导体器件测试仪器

    公开(公告)号：US6016565A

    公开(公告)日：2000-01-18

    申请号：US874669

    申请日：1997-06-13

    Applicant: Takeo Miura

    Inventor： Takeo Miura

    IPC: G01R31/319 ,  G01R31/3193 ,  G01R31/28

    CPC classification number: G01R31/31937 ,  G01R31/31922

    Abstract: A strobe generator includes four strobe pulse generators generating original strobe pulses having the same frequency, respectively, and correspondingly, four logical comparator circuits, the number of which is identical to that of the strobe pulse generators. Further, a mode selection circuit is provided which can set any one of mode 1, mode 2 and mode 3. In mode 1, an output signal V from a level comparator is latched by a new high speed strobe signal having a frequency four times the frequency of the original strobe pulse, and the latched signals are sequentially compared with expected value data signals. In mode 2, an output signal V from the level comparator is latched by two new high speed strobe signals having a frequency two times the frequency of the original strobe pulse, and the latched signals are sequentially compared with the expected value data signals. In mode 3, an output signal V from the level comparator is latched by four new strobe signals having the same frequency as the frequency of the original strobe pulse and different phases from one another, and the latched signals are sequentially compared with the expected value data signals.

    Abstract translation: 选通发生器包括四个选通脉冲发生器，分别产生具有相同频率的原始选通脉冲，相应地，四个逻辑比较器电路的数量与选通脉冲发生器的数量相同。 此外，提供了可以设置模式1，模式2和模式3中的任何一个的模式选择电路。在模式1中，来自电平比较器的输出信号V被新的高速选通信号锁存，频率为频率的四倍 原始选通脉冲的频率和锁存信号与期望值数据信号顺序地比较。 在模式2中，来自电平比较器的输出信号V被两个具有原始选通脉冲的频率的两倍的新的高速选通信号锁存，并且锁存的信号被顺序地与预期值数据信号进行比较。 在模式3中，来自电平比较器的输出信号V被四个具有与原始选通脉冲的频率相同的频率和不同相位的新的选通信号锁存，并且锁存的信号被顺序地与预期值数据进行比较 信号。

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