公开(公告)号：US5311476A

公开(公告)日：1994-05-10

申请号：US943341

申请日：1992-06-18

申请人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

发明人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K3/037 ,  H03K19/096

CPC分类号： G11C29/027 ,  G11C11/406 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004

摘要： There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input terminal, and a test mode can be effected in which the refresh period can be set at an optional value by accordingly applying a test control signal to a predetermined external terminal. Therefore, the discharge current of the oscillation circuit capacitor associated with the refresh timer circuit becomes stabilized, noting the particular layout arrangement regarding the polycrystalline silicon layer forming the resistor of the oscillation circuit, and the fact that same parasitic capacitances are effectively connected between the polycrystalline silicon resistor and the supply voltage of the circuit and between the polycrystalline silicon resistor and the ground potential of the circuit thereby cancelling any variation of the output of the power source. Therefore, variation of the oscillation frequency of the oscillation circuit attributable to the bumping of the power source can be effectively suppressed.

公开(公告)号：US5467315A

公开(公告)日：1995-11-14

申请号：US234414

申请日：1994-04-28

申请人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

发明人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K3/037 ,  H03K19/096 ,  G11C7/00

CPC分类号： G11C29/027 ,  G11C11/406 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004

摘要： The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal. Such availability of plural self-refresh modes becomes particularly advantageous when considering consumption of the back-up power for maintaining the IC memory device versus stability of stored data. While the consumption of the back-up power for maintaining the device would be relatively lower under one of the self-refresh modes, namely, the PS (pseudo) refresh mode, the stability of data stored would, however, be greater under another self-refresh mode, namely, the VS (virtual) refresh mode.

摘要翻译： 利用用于实现分别具有不同刷新周期的多个自刷新模式的控制电路来促进半导体存储器。 多个自刷新模式以PS（伪）刷新模式为代表，当存储器处于非选择状态较长时间段时，例如在便于存储器备份的状态下，以及由 在存储器访问的间隔期间间歇地执行存储器单元的刷新操作的VS（虚拟）刷新模式。 伪刷新模式具有比虚拟刷新模式更长的刷新时间段。 控制电路还具有用于根据指示伪刷新模式的第一定时信号和指示虚拟刷新模式的第二定时信号产生刷新地址信号的计数器电路，后一定时信号是较高频率信号。 当考虑用于维持IC存储器件的备用电源与存储的数据的稳定性的消耗时，这种多重自刷新模式的可用性变得特别有利。 虽然在自刷新模式之一（即PS）（伪）刷新模式下，用于维持设备的备份功率的消耗将相对较低，但是存储的数据的稳定性在另一个自身下将更大 - 刷新模式，即VS（虚拟）刷新模式。

公开(公告)号：US5161120A

公开(公告)日：1992-11-03

申请号：US496531

申请日：1990-03-20

申请人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

发明人： Takeshi Kajimoto ,  Yutaka Shimbo ,  Katsuyuki Sato ,  Masahiro Ogata ,  Kanehide Kenmizaki ,  Shouji Kubono ,  Nobuo Kato ,  Kiichi Manita ,  Michitaro Kanamitsu

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/00 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H03K3/037 ,  H03K19/096

CPC分类号： G11C29/027 ,  G11C11/406 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004

摘要： A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.

摘要翻译： 数据输出缓冲器与诸如伪稳态RAM的半导体存储器相关地提供，其能够相对于存储器数据读出而进行高速操作。 该缓冲器包括一个锁存电路，该锁存电路包括一对具有交叉连接的输入和输出端的NAND门电路，分别设置在锁存电路的非反相和反相输入端之间的一对预充电MOSFET，一对转换 根据反相定时信号的锁存电路的反相信号和实现上拉/下拉布置的一对串联MOSFET，其接收NAND门输出信号的反相信号。