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公开(公告)号：US07939908B2
公开(公告)日：2011-05-10
申请号：US11510584
申请日：2006-08-28
IPC分类号： H01L21/76
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
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2.发明授权Semiconductor integrated circuit device having nonvolatile semiconductor memory and programming method thereof 失效具有非易失性半导体存储器的半导体集成电路器件及其编程方法公开(公告)号：US07369439B2
公开(公告)日：2008-05-06
申请号：US11397725
申请日：2006-04-05
申请人： Takeshi Kamigaichi , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Kikuko Sugimae
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C2216/14 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of memory cell transistors arranged in a matrix form. The device further includes a high-voltage circuit area arranged in a peripheral area of the memory cell array and including a first high-voltage transistor having a current path which is connected at one end to a selected control gate and a second high-voltage transistor having a current path which is connected at one end to a first non-selected control gate adjacent to the selected control gate and configured to raise voltage applied to the selected control gate to program voltage by use of first capacitive coupling caused between the selected control gate and the first non-selected control gate by applying intermediate voltage approximately equal to voltage which makes the current path of the memory cell transistor conductive to the first non-selected control gate.
摘要翻译： 半导体集成电路器件包括具有以矩阵形式布置的多个存储单元晶体管的存储单元阵列。 该装置还包括布置在存储单元阵列的外围区域中的高压电路区域，并且包括具有电流路径的第一高压晶体管，该电流路径一端连接到选定的控制栅极和第二高压晶体管 具有电流路径，其一端连接到与所选择的控制栅极相邻的第一未选择的控制栅极，并且被配置为通过使用在所选择的控制栅极之间产生的第一电容耦合来提高施加到所选择的控制栅极的编程电压 以及通过施加近似等于使存储单元晶体管的电流路径导通到第一未选择的控制栅极的电压的中间电压而使第一未选择的控制栅极。
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3.发明申请Semiconductor integrated circuit device having nonvolatile semiconductor memory and programming method thereof 失效具有非易失性半导体存储器的半导体集成电路器件及其编程方法公开(公告)号：US20060239069A1
公开(公告)日：2006-10-26
申请号：US11397725
申请日：2006-04-05
申请人： Takeshi Kamigaichi , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Kikuko Sugimae
CPC分类号： G11C16/10 , G11C16/0483 , G11C2216/14 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of memory cell transistors arranged in a matrix form. The device further includes a high-voltage circuit area arranged in a peripheral area of the memory cell array and including a first high-voltage transistor having a current path which is connected at one end to a selected control gate and a second high-voltage transistor having a current path which is connected at one end to a first non-selected control gate adjacent to the selected control gate and configured to raise voltage applied to the selected control gate to program voltage by use of first capacitive coupling caused between the selected control gate and the first non-selected control gate by applying intermediate voltage approximately equal to voltage which makes the current path of the memory cell transistor conductive to the first non-selected control gate.
摘要翻译： 半导体集成电路器件包括具有以矩阵形式布置的多个存储单元晶体管的存储单元阵列。 该装置还包括布置在存储单元阵列的外围区域中的高压电路区域，并且包括具有电流路径的第一高压晶体管，该电流路径一端连接到选定的控制栅极和第二高压晶体管 具有电流路径，其一端连接到与所选择的控制栅极相邻的第一未选择的控制栅极，并且被配置为通过使用在所选择的控制栅极之间产生的第一电容耦合来提高施加到所选择的控制栅极的编程电压 以及通过施加近似等于使存储单元晶体管的电流路径导通到第一未选择的控制栅极的电压的中间电压而使第一未选择的控制栅极。
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公开(公告)号：US20050073001A1
公开(公告)日：2005-04-07
申请号：US10892445
申请日：2004-07-16
IPC分类号： G11C16/06 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/4236 , H01L29/7881
摘要： This nonvolatile semiconductor memory includes: a first and a second memory cell column having memory cell transistors connected in series with a floating gate and a first and a second control gate located at both sides of that floating gate; a first select-gate transistor connected between the first memory cell column and a bit line; a second select-gate transistor connected between the second memory cell column and the bit line; and a third select gate transistor connected between the first memory cell column and a source line and also between the second memory cell column and the source line, respectively.
摘要翻译： 该非易失性半导体存储器包括：具有与浮动栅极串联连接的存储单元晶体管的第一和第二存储单元列以及位于该浮置栅极两侧的第一和第二控制栅极; 连接在第一存储单元列和位线之间的第一选择栅晶体管; 连接在第二存储单元列和位线之间的第二选择栅晶体管; 以及分别连接在第一存储单元列和源极线之间以及第二存储单元列和源极线之间的第三选择栅极晶体管。
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公开(公告)号：US08482095B2
公开(公告)日：2013-07-09
申请号：US13086478
申请日：2011-04-14
IPC分类号： H01L21/76
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
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6.发明授权Semiconductor integrated circuit device including memory cells having floating gates and resistor elements 有权包括具有浮动栅极和电阻元件的存储单元的半导体集成电路器件公开(公告)号：US07906816B2
公开(公告)日：2011-03-15
申请号：US11346292
申请日：2006-02-03
申请人： Kikuko Sugimae , Takeshi Kamigaichi
发明人： Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L27/11
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531
摘要： A semiconductor integrated circuit device includes an element isolation region which is formed in a semiconductor substrate to isolate an element region of the semiconductor substrate, memory cells having floating gates and formed on the element region, and resistor elements formed on the element region. The floating gate has a laminated structure containing a plurality of conductive films. The resistor element has a contact portion for connection with a wiring and a resistor portion acting as a resistor. The resistor portion has a laminated structure having at least one of the plurality of conductive films and an insulating material having a selective etching ratio with respect to the semiconductor substrate.
摘要翻译： 半导体集成电路器件包括形成在半导体衬底中以隔离半导体衬底的元件区域的元件隔离区域，具有形成在元件区域上的浮动栅极的存储单元以及形成在元件区域上的电阻器元件。 浮栅具有包含多个导电膜的层叠结构。 电阻元件具有用于与布线连接的接触部分和用作电阻器的电阻部分。 电阻部分具有层叠结构，其具有多个导电膜中的至少一个和相对于半导体衬底具有选择性蚀刻比的绝缘材料。
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公开(公告)号：US07405440B2
公开(公告)日：2008-07-29
申请号：US10983744
申请日：2004-11-09
IPC分类号： H01L29/788
CPC分类号： G11C5/025 , G11C16/04 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A nonvolatile semiconductor memory on a semiconductor chip includes: a cell array region configured with a memory cell transistor having a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a floating gate electrode adjacent to the first control gate electrode; a high voltage circuit region including a high voltage transistor made of a second metallic salicide film, a first source region and a first drain region, and a first gate region arranged between the first source region and the first drain region; and a low voltage circuit region including a low voltage transistor made of a third metallic salicide film, a second source region and a second drain region electrically coupled with the third metallic salicide film, and a second gate region arranged between the second source region and the second drain region and is electrically coupled with the third metallic salicide film.
摘要翻译： 半导体芯片上的非易失性半导体存储器包括：单元阵列区域，其配置有具有第一金属自对离硅化物膜的存储单元晶体管，与第一金属硅化物膜电耦合的第一控制栅电极和与第一金属化物质相邻的浮置栅电极 控制栅电极; 包括由第二金属硅化物膜制成的高压晶体管，第一源极区和第一漏极区以及布置在第一源极区和第一漏极区之间的第一栅极区的高电压电路区; 以及包括由第三金属硅化物膜制成的低压晶体管的低电压电路区域，与第三金属硅化物膜电耦合的第二源极区域和第二漏极区域，以及布置在第二源极区域和第二源极区域之间的第二栅极区域 第二漏区，并与第三金属硅化物膜电耦合。
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公开(公告)号：US20070013024A1
公开(公告)日：2007-01-18
申请号：US11510584
申请日：2006-08-28
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
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公开(公告)号：US20110193152A1
公开(公告)日：2011-08-11
申请号：US13086478
申请日：2011-04-14
IPC分类号： H01L27/115 , H01L27/105
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
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公开(公告)号：US07119413B2
公开(公告)日：2006-10-10
申请号：US10967128
申请日：2004-10-19
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
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