公开(公告)号：US09128704B2

公开(公告)日：2015-09-08

申请号：US12352166

申请日：2009-01-12

申请人： Takeshi Kato ,  Tadakatsu Nakajima ,  Tatsuya Saito ,  Jun Okitsu ,  Yoko Shiga ,  Yoshio Miki

发明人： Takeshi Kato ,  Tadakatsu Nakajima ,  Tatsuya Saito ,  Jun Okitsu ,  Yoko Shiga ,  Yoshio Miki

IPC分类号： G06F1/32 ,  G06F1/20 ,  G05B19/042

CPC分类号： G06F1/28 ,  G05B19/042 ,  G05B2219/25387 ,  G05B2219/2614 ,  G05B2219/2638 ,  G06F1/20 ,  G06F1/3203

摘要： Total power consumption of information-processing devices and power supply/cooling facilities is reduced to realize energy saving operation of information-processing system. The information-processing system includes information-processing devices, power supply facilities, cooling facilities and an operations management device. The operations management device is connected to the devices and the facilities and includes layout information constituted of locations and operating information of the devices and locations and environmental information of the facilities. Also, the operations management device obtains the power consumption of the devices, the power supply loss of the power supply facilities and the cooling power of the cooling facilities by using the layout information, and then allocates the workloads to the devices so as to reduce the total sum of power consumption, supply loss and cooling power.

摘要翻译： 信息处理设备和电源/冷却设备的总耗电量减少，实现信息处理系统的节能运行。 信息处理系统包括信息处理设备，电源设备，冷却设备和操作管理设备。 操作管理装置连接到设备和设施，并且包括由设备的位置和操作信息以及设施的位置和环境信息构成的布局信息。 此外，操作管理装置通过使用布局信息获得设备的功耗，电源设备的电源损耗和冷却设备的冷却功率，然后将工作负载分配给设备，以减少 功耗，供电损耗和冷却功率的总和。

公开(公告)号：US20090259345A1

公开(公告)日：2009-10-15

申请号：US12352166

申请日：2009-01-12

申请人： Takeshi Kato ,  Tadakatsu Nakajima ,  Tatsuya Saito ,  Jun Okitsu ,  Yoko Shiga ,  Yoshio Miki

发明人： Takeshi Kato ,  Tadakatsu Nakajima ,  Tatsuya Saito ,  Jun Okitsu ,  Yoko Shiga ,  Yoshio Miki

IPC分类号： G06F1/30 ,  G06F9/50 ,  G06F9/455 ,  G06F15/177

CPC分类号： G06F1/28 ,  G05B19/042 ,  G05B2219/25387 ,  G05B2219/2614 ,  G05B2219/2638 ,  G06F1/20 ,  G06F1/3203

摘要： Total power consumption of information-processing devices and power supply/cooling facilities is reduced to realize energy saving operation of information-processing system. The information-processing system includes information-processing devices, power supply facilities, cooling facilities and an operations management device. The operations management device is connected to the devices and the facilities and includes layout information constituted of locations and operating information of the devices and locations and environmental information of the facilities. Also, the operations management device obtains the power consumption of the devices, the power supply loss of the power supply facilities and the cooling power of the cooling facilities by using the layout information, and then allocates the workloads to the devices so as to reduce the total sum of power consumption, supply loss and cooling power.

摘要翻译： 信息处理设备和电源/冷却设备的总耗电量减少，实现信息处理系统的节能运行。 信息处理系统包括信息处理设备，电源设备，冷却设备和操作管理设备。 操作管理装置连接到设备和设施，并且包括由设备的位置和操作信息以及设施的位置和环境信息构成的布局信息。 此外，操作管理装置通过使用布局信息获得设备的功耗，电源设备的电源损耗和冷却设备的冷却功率，然后将工作负载分配给设备，以减少 功耗，供电损耗和冷却功率的总和。

公开(公告)号：US5881078A

公开(公告)日：1999-03-09

申请号：US989414

申请日：1997-12-12

申请人： Makoto Hanawa ,  Yoshio Miki ,  Tatsuya Kawashimo

发明人： Makoto Hanawa ,  Yoshio Miki ,  Tatsuya Kawashimo

IPC分类号： G06F11/00 ,  G06F11/08 ,  H03K19/00

CPC分类号： G06F11/085

摘要： Soft errors generated at an active time are reduced by adding a small-scale circuit to a high performance LSI, such as a processor without reducing the performance of the circuit. The processor has individual logic circuits each having a plurality of stages of logic gates for outputting true signals and complement signals for the individual logic gates. A latch circuit latches the true and complement signals of the logic circuits separately and a compare circuit detects for an error by comparing the true and complement output signals of the logic circuits to determine if they are at the same logical signal level or not, just upstream of the latch in which the individual true and complement output signals of the final logic circuit stages are individually latched. When the compare circuit detects an error because the true and complement output signals are at the same logical signal level, a recovery process is executed.

摘要翻译： 通过向诸如处理器的高性能LSI添加小规模电路而不降低电路的性能来减少在活动时间产生的软错误。 处理器具有各自具有用于输出各个逻辑门的真实信号和补码信号的多级逻辑门的单独逻辑电路。 锁存电路分别锁存逻辑电路的真实和补码信号，比较电路通过比较逻辑电路的真实和补码输出信号来确定它们是否处于相同的逻辑信号电平，正好在上游 其中最终逻辑电路级的各个真实和补码输出信号被单独锁存。 当比较电路检测到误差是因为真实和补码输出信号处于相同的逻辑信号电平时，执行恢复处理。

公开(公告)号：US08635241B2

公开(公告)日：2014-01-21

申请号：US13148966

申请日：2009-02-18

申请人： Yasuhide Mori ,  Yoshio Miki ,  Masahiro Kato

发明人： Yasuhide Mori ,  Yoshio Miki ,  Masahiro Kato

IPC分类号： G06F17/00

CPC分类号： G06F17/3087

摘要： Provided is an information recommendation system capable of recommending an unexpected item which a user is interested in but cannot assume easily. A server gives one or more times of initial recommendations of recommending information by a means of a user profile and a behavior history, and narrows down second recommended items to recommend next by using not only information relating to items having responses but also information relating to items having no response together. In narrowing down, the items are arranged by means of an item arrangement program by using the results of the initial recommendations, and it is identified depending on similarity by means of a boundary calculation program where the boundary between user's interest and no interest is positioned in all the items. Then, it is identified where items not recommended yet are positioned in user's interest/no interest the areas, and items in the vicinity of the boundary between the interest and no interest are determined as the second recommended items which are not uninterested and maximize unexpectedness.

摘要翻译： 提供了能够推荐用户感兴趣但不能容易地假设的意外项目的信息推荐系统。 服务器通过用户个人资料和行为历史提供一次或多次初次推荐信息，并缩小第二个推荐项目，以便不仅使用与具有响应的项目​​相关的信息，而且还使用与项目有关的信息 一起没有回应 在缩小时，通过使用初始建议的结果，通过项目安排程序来排列项目，并且通过边界计算程序根据相似性来确定项目，其中用户兴趣和不感兴趣之间的边界位于 所有的项目。 然后，确定哪些物品不被推荐的位置是用户的兴趣/没有利益的区域，并且利息和无利益之间的边界附近的项目被确定为不感兴趣的并且最大化意外的第二推荐项目。

公开(公告)号：US20110314040A1

公开(公告)日：2011-12-22

申请号：US13148966

申请日：2009-02-18

申请人： Yasuhide Mori ,  Yoshio Miki ,  Masahiro Kato

发明人： Yasuhide Mori ,  Yoshio Miki ,  Masahiro Kato

IPC分类号： G06F17/30

CPC分类号： G06F17/3087

摘要： Provided is an information recommendation system capable of recommending an unexpected item which a user is interested in but cannot assume easily. A server gives one or more times of initial recommendations of recommending information by a means of a user profile and a behavior history, and narrows down second recommended items to recommend next by using not only information relating to items having responses but also information relating to items having no response together. In narrowing down, the items are arranged by means of an item arrangement program by using the results of the initial recommendations, and it is identified depending on similarity by means of a boundary calculation program where the boundary between user's interest and no interest is positioned in all the items. Then, it is identified where items not recommended yet are positioned in user's interest/no interest the areas, and items in the vicinity of the boundary between the interest and no interest are determined as the second recommended items which are not uninterested and maximize unexpectedness.

摘要翻译： 提供了能够推荐用户感兴趣但不能容易地假设的意外项目的信息推荐系统。 服务器通过用户个人资料和行为历史提供一次或多次初次推荐信息，并缩小第二个推荐项目，以便不仅使用与具有响应的项目​​相关的信息，而且还使用与项目有关的信息 一起没有回应 在缩小时，通过使用初始建议的结果，通过项目安排程序来排列项目，并且通过边界计算程序根据相似性来确定项目，其中用户兴趣和不感兴趣之间的边界位于 所有的项目。 然后，确定哪些物品不被推荐的位置是用户的兴趣/没有利益的区域，并且利息和无利益之间的边界附近的项目被确定为不感兴趣的并且最大化意外的第二推荐项目。

公开(公告)号：US20050160407A1

公开(公告)日：2005-07-21

申请号：US10933218

申请日：2004-09-03

申请人： Akihiro Takamura ,  Yoshio Miki

发明人： Akihiro Takamura ,  Yoshio Miki

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F9/455

CPC分类号： G06F9/455

摘要： For reducing instruction cache misses in emulation by a dynamic conversion method, it is judged whether or not instruction cache conflict with a portion of an emulation program, whose execution frequency is high, occurs in an emulation operation, and only addresses not bringing about cache conflict are set as converted instruction storing areas. Thereby, instruction cache misses in a dynamic conversion type emulator are reduced, and the emulation speed is improved.

摘要翻译： 为了通过动态转换方法减少仿真中的指令高速缓存未命中，判断在仿真操作中是否发生指令高速缓冲存储器与执行频率高的仿真程序的一部分冲突，并且仅存在不引起缓存冲突的地址 被设置为转换指令存储区域。 因此，动态转换型仿真器中的指令高速缓存未命中被减少，仿真速度提高。

公开(公告)号：US4699938A

公开(公告)日：1987-10-13

申请号：US848186

申请日：1986-04-04

申请人： Yoshihiro Minamizaki ,  Yoshio Miki ,  Takayuki Yamamoto ,  Akira Iio ,  Toshinori Sakagami

发明人： Yoshihiro Minamizaki ,  Yoshio Miki ,  Takayuki Yamamoto ,  Akira Iio ,  Toshinori Sakagami

IPC分类号： C08F297/00 ,  C08F297/02 ,  C08F297/04 ,  C09J7/02 ,  C09J153/00 ,  C09J153/02 ,  C08L53/02

CPC分类号： C09J153/02 ,  C09J7/0221

摘要： A pressure-sensitive adhesive composition comprising as a base polymer a mixed block copolymer comprising a polymer block of a monovinyl-substituted aromatic compound and a polymer block of a conjugated diene compound. The pressure-sensitive adhesive composition is useful to seal, for example, corrugated board or carton.

摘要翻译： 一种压敏粘合剂组合物，其包含作为基础聚合物的混合嵌段共聚物，其包含单乙烯基取代的芳族化合物的聚合物嵌段和共轭二烯化合物的聚合物嵌段。 压敏粘合剂组合物可用于密封例如瓦楞纸板或纸箱。

公开(公告)号：US06259383B1

公开(公告)日：2001-07-10

申请号：US09267596

申请日：1999-03-15

申请人： Yoshio Miki

发明人： Yoshio Miki

IPC分类号： H03M500

CPC分类号： H03M5/00

摘要： In the transmission of a logic signal, there is a reduced maximum value and a reduced average value of the number of bits varied by transforming an input level representation original logic signal having n bits into a transition representation logic signal of m groups with only a maximum of k bits varied, wherein k and m are integer numbers, n is greater than k and each value of k and m is greater than 1. The transformed logic signal of m groups is transmitted. The transmitted logic signal of m groups is then transformed into the original logic signal having n bits. A maximum number of bits varied is k, which can be below n/2 as a maximum, which is less than an average bit variation of the input original signal.

摘要翻译： 在逻辑信号的发送中，通过将具有n位的输入电平表示原始逻辑信号变换为仅具有最大值的m个组的转换表示逻辑信号，存在减小的最大值和减少的位数的平均值 k位变化，其中k和m是整数，n大于k，k和m的每个值都大于1. m组的变换逻辑信号被发送。 然后将m组的发送逻辑信号变换为具有n位的原始逻辑信号。 变化的最大位数为k，其可以低于最小值的n / 2，小于输入原始信号的平均位变化。

公开(公告)号：US5761076A

公开(公告)日：1998-06-02

申请号：US812441

申请日：1997-03-06

申请人： Yoshio Miki

发明人： Yoshio Miki

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5081 ,  G06F17/5022

摘要： The sum of capacitance is determined by an LSI load characteristic extraction program 217, as for the capacitance of a plurality of wiring patterns constituting different segments of a wiring, between the wiring and a plurality of other wiring patterns adjacent to the wiring, and the resistance of each wiring pattern also is determined. On the basis of the resistance and capacitance, a load characteristic value 222 comprised of a plurality of predetermined lower order coefficients of series expansion of complex admittance at the driving point of that wiring is calculated. A delay calculation program 223 calculates delay time and power dissipation as the driving characteristic of logic gates which drive this wiring, according to the coefficients and a device characteristic library 212. The library 212 is generated in advance by a program 600, in which a plurality or lower order coefficients of series expansion obtained by series expanding the complex admittance of a plurality of wirings of different length, the delay time and power dissipation of a device when driving these wirings by that device are maintained. For evaluating the capacitance of respective wiring patterns, by dividing the substrate into a plurality of regions, using a region management table for registering a plurality of wiring patterns for each region, and detecting wiring patterns in the same region, the capacitance therebetween is calculated.

摘要翻译： 对于构成布线的不同部分的多个布线图案的电容，布线与与布线相邻的多个其它布线图案之间，电容的总和由LSI负载特性提取程序217确定，并且电阻 的每个布线图案也被确定。 基于电阻和电容，计算由在该布线的驱动点处的复数导纳的多个预定的较低阶系数扩展构成的负载特性值222。 延迟计算程序223根据系数和设备特征库212，计算延迟时间和功耗作为驱动该布线的逻辑门的驱动特性。库212由程序600预先生成，其中多个 或通过串联扩展不同长度的多个布线的复合导纳而获得的串联扩展的较低阶系数，保持由该器件驱动这些布线时器件的延迟时间和功耗。 为了评估各布线图案的电容，通过使用用于登记各区域的多个布线图案的区域管理表，并且检测相同区域中的布线图案，计算其间的电容。

公开(公告)号：US5753441A

公开(公告)日：1998-05-19

申请号：US488011

申请日：1996-01-05

申请人： Mark H. Skolnick ,  David E. Goldgar ,  Yoshio Miki ,  Jeff Swenson ,  Alexander Kamb ,  Keith D. Harshman ,  Donna M. Shattuck-Eidens ,  Sean V. Tavtigian ,  Roger W. Wiseman ,  P. Andrew Futreal

发明人： Mark H. Skolnick ,  David E. Goldgar ,  Yoshio Miki ,  Jeff Swenson ,  Alexander Kamb ,  Keith D. Harshman ,  Donna M. Shattuck-Eidens ,  Sean V. Tavtigian ,  Roger W. Wiseman ,  P. Andrew Futreal

IPC分类号： A61K38/00 ,  A61K48/00 ,  C07K14/47 ,  C07K14/82 ,  C12Q1/68 ,  C07H21/02 ,  C07H21/04 ,  C12P19/34

CPC分类号： C07K14/82 ,  C07K14/4703 ,  C12Q1/6886 ,  A01K2217/05 ,  A61K38/00 ,  A61K48/00 ,  C12Q2600/156 ,  C12Q2600/172

摘要： The present invention relates generally to the field of human genetics. Specifically, the present invention relates to methods and materials used to isolate and detect a human breast and ovarian cancer predisposing gene (BRCA1), some mutant alleles of which cause susceptibility to cancer, in particular breast and ovarian cancer. More specifically, the invention relates to germline mutations in the BRCA1 gene and their use in the diagnosis of predisposition to breast and ovarian cancer. The present invention further relates to somatic mutations in the BRCA1 gene in human breast and ovarian cancer and their use in the diagnosis and prognosis of human breast and ovarian cancer. Additionally, the invention relates to somatic mutations in the BRCA1 gene in other human cancers and their use in the diagnosis and prognosis of human cancers. The invention also relates to the therapy of human cancers which have a mutation in the BRCA1 gene, including gene therapy, protein replacement therapy and protein mimetics. The invention further relates to the screening of drugs for cancer therapy. Finally, the invention relates to the screening of the BRCA1 gene for mutations, which are useful for diagnosing the predisposition to breast and ovarian cancer.

摘要翻译： 本发明一般涉及人类遗传学领域。 具体地，本发明涉及用于分离和检测人乳腺癌和卵巢癌易感基因（BRCA1）的一些突变等位基因，特别是乳腺癌和卵巢癌的易感性的突变等位基因的方法和材料。 更具体地，本发明涉及BRCA1基因中的种系突变及其在诊断乳腺癌和卵巢癌易感性中的用途。 本发明还涉及人乳腺癌和卵巢癌中BRCA1基因的体细胞突变及其在人乳腺癌和卵巢癌诊断和预后中的应用。 另外本发明涉及其他人类癌症中BRCA1基因的体细胞突变及其在人类癌症诊断和预后中的应用。 本发明还涉及在BRCA1基因中具有突变的人类癌症的治疗，包括基因治疗，蛋白质替代疗法和蛋白质模拟物。 本发明还涉及用于癌症治疗的药物的筛选。 最后，本发明涉及用于突变的BRCA1基因的筛选，其可用于诊断乳腺和卵巢癌的易感性。