公开(公告)号：US08586468B2

公开(公告)日：2013-11-19

申请号：US11210586

申请日：2005-08-24

申请人： Takeshi Nogami ,  Masanaga Fukasawa

发明人： Takeshi Nogami ,  Masanaga Fukasawa

IPC分类号： H01L21/28

CPC分类号： H01L21/76898 ,  B82Y10/00 ,  H01L23/481 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： An arrangement of semiconductor chips is provided. The arrangement includes a plurality of stacked semiconductor chips each including an integrated circuit. At least one via is formed through the thickness of at least one of the semiconductor chips. A carbon nanotube conductor is formed in the via. The conductor has first and second opposite ends. The first end of the conductor is selectively interconnected with the integrated circuit of its semiconductor chip and the second end of the conductor is selectively interconnected with the integrated circuit of another of the semiconductor chips.

摘要翻译： 提供了半导体芯片的布置。 该装置包括多个堆叠的半导体芯片，每个堆叠的半导体芯片均包括集成电路。 通过至少一个半导体芯片的厚度形成至少一个通孔。 在通孔中形成碳纳米管导体。 导体具有第一和第二相对端。 导体的第一端与其半导体芯片的集成电路选择性地互连，并且导体的第二端选择性地与另一个半导体芯片的集成电路互连。

公开(公告)号：US20070232047A1

公开(公告)日：2007-10-04

申请号：US11395829

申请日：2006-03-31

申请人： Masanaga Fukasawa ,  Takeshi Nogami

发明人： Masanaga Fukasawa ,  Takeshi Nogami

IPC分类号： H01L21/44

CPC分类号： H01L21/3105 ,  H01L21/31058 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826

摘要： A method of fabricating a damascene interconnection is provided. The method begins by forming on a substrate a low k dielectric layer and a resist pattern over the low k dielectric layer to define a first interconnect opening. The low k dielectric layer is etched through the resist pattern to form the first interconnect opening, whereby damage arises to a portion of the low k dielectric layer defining a sidewall of the first interconnect opening. The resist pattern is then removed and a barrier layer is applied to line the first interconnect opening. An interconnection is formed by filling the first interconnect opening with a conductive material. The interconnection is planarized to remove excess material, whereby an underlying portion of the low k dielectric layer is damaged during planarizing. The damaged underlying portion of the low k dielectric layer and the damaged sidewall portion of the low k dielectric layer are both repaired at least in part after performing the planarizing step.

摘要翻译： 提供了一种制造镶嵌互连的方法。 该方法开始于在衬底上形成低k电介质层和在低k电介质层上的抗蚀剂图案以限定第一互连开口。 通过抗蚀剂图案蚀刻低k电介质层以形成第一互连开口，由此限定第一互连开口的侧壁的低k电介质层的一部分产生损伤。 然后去除抗蚀剂图案，并且施加阻挡层以使第一互连开口线对。 通过用导电材料填充第一互连开口形成互连。 互连被平坦化以去除多余的材料，由此低k电介质层的下层部分在平坦化期间被损坏。 在执行平坦化步骤之后，至少部分地修复低k电介质层的损坏的底层部分和低k电介质层的损坏的侧壁部分。

公开(公告)号：US20070231993A1

公开(公告)日：2007-10-04

申请号：US11394011

申请日：2006-03-30

申请人： Masanaga Fukasawa ,  Takeshi Nogami

发明人： Masanaga Fukasawa ,  Takeshi Nogami

IPC分类号： H01L21/8238

CPC分类号： H01L21/76829 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening. The capping layer and the dielectric layer are etched through the resist pattern to form the first interconnect opening. The resist pattern is removed and a barrier layer is applied over the capping layer and in the first interconnect opening. An interconnection is formed by filling the first interconnect opening with conductive material. The interconnection is planarized to remove excess material and a portion of the first dielectric layer damaged by the planarizing step is selectively etched. A second dielectric layer is applied to replace the damaged portion of the first dielectric.

公开(公告)号：US07300868B2

公开(公告)日：2007-11-27

申请号：US11394011

申请日：2006-03-30

申请人： Masanaga Fukasawa ,  Takeshi Nogami

发明人： Masanaga Fukasawa ,  Takeshi Nogami

IPC分类号： H01L21/4763

CPC分类号： H01L21/76829 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening. The capping layer and the dielectric layer are etched through the resist pattern to form the first interconnect opening. The resist pattern is removed and a barrier layer is applied over the capping layer and in the first interconnect opening. An interconnection is formed by filling the first interconnect opening with conductive material. The interconnection is planarized to remove excess material and a portion of the first dielectric layer damaged by the planarizing step is selectively etched. A second dielectric layer is applied to replace the damaged portion of the first dielectric.

摘要翻译： 提供了一种制造镶嵌互连的方法。 该方法开始于在衬底上形成第一电介质层，第一电介质子层上的覆盖层和覆盖层上的抗蚀剂图案以限定第一互连开口。 通过抗蚀剂图案蚀刻覆盖层和电介质层以形成第一互连开口。 去除抗蚀剂图案，并且在封盖层和第一互连开口中施加阻挡层。 通过用导电材料填充第一互连开口形成互连。 互连被平坦化以去除多余的材料，并且选择性地蚀刻由平坦化步骤损坏的第一介电层的一部分。 施加第二介电层以代替第一电介质的损坏部分。

公开(公告)号：US20070045762A1

公开(公告)日：2007-03-01

申请号：US11210586

申请日：2005-08-24

申请人： Takeshi Nogami ,  Masanaga Fukasawa

发明人： Takeshi Nogami ,  Masanaga Fukasawa

IPC分类号： H01L31/00

CPC分类号： H01L21/76898 ,  B82Y10/00 ,  H01L23/481 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： An arrangement of semiconductor chips is provided. The arrangement includes a plurality of stacked semiconductor chips each including an integrated circuit. At least one via is formed through the thickness of at least one of the semiconductor chips. A carbon nanotube conductor is formed in the via. The conductor has first and second opposite ends. The first end of the conductor is selectively interconnected with the integrated circuit of its semiconductor chip and the second end of the conductor is selectively interconnected with the integrated circuit of another of the semiconductor chips.

摘要翻译： 提供了半导体芯片的布置。 该装置包括多个堆叠的半导体芯片，每个堆叠的半导体芯片均包括集成电路。 通过至少一个半导体芯片的厚度形成至少一个通孔。 在通孔中形成碳纳米管导体。 导体具有第一和第二相对端。 导体的第一端与其半导体芯片的集成电路选择性地互连，并且导体的第二端选择性地与另一个半导体芯片的集成电路互连。

公开(公告)号：US08969197B2

公开(公告)日：2015-03-03

申请号：US13475526

申请日：2012-05-18

申请人： Daniel C. Edelstein ,  Takeshi Nogami ,  Christopher Parks ,  Tsong-Lin Tai

发明人： Daniel C. Edelstein ,  Takeshi Nogami ,  Christopher Parks ,  Tsong-Lin Tai

IPC分类号： H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/53209 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/76 ,  H01L24/82 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

摘要翻译： 具有改进的电迁移阻力的结构及其制造方法。 具有改进的电迁移电阻的结构包括具有双层盖和介电覆盖层的体互连。 双层帽包括底部金属部分和顶部金属氧化物部分。 优选地，金属氧化物部分是MnO或MnSiO，金属部分是Mn或CuMn。 通过用杂质（在优选实施例中为Mn）掺杂互连，然后在互连的顶部处产生晶格缺陷来产生该结构。 这些缺陷驱使增加的杂质向互连顶表面迁移。 当形成电介质盖层时，一部分与分离的杂质反应，从而在互连上形成双层盖。 Cu表面的晶格缺陷可以通过等离子体处理，离子注入，压缩薄膜或其他方式产生。

公开(公告)号：US08841212B2

公开(公告)日：2014-09-23

申请号：US13609668

申请日：2012-09-11

申请人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Thomas M. Shaw ,  Andrew H. Simon ,  Jean E. Wynne ,  Chih-Chao Yang

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.

摘要翻译： 一种方法图形为多级集成电路结构的低K绝缘体层中的至少一个开口，使得铜导体在开口的底部露出。 该方法然后在第一室中用第一钽氮化物层排列开口的侧壁和底部，并在第一室中的第一氮化钽层上形成钽层。 接下来，在第一室中进行对开口的溅射蚀刻，以使开口底部的导体露出。 在第一室中再次在导体，钽层和第一氮化钽层上形成第二钽氮化物层。 在形成第二钽氮化物层之后，本文的方法在第二不同室中在第二氮化钽层上形成包含铂族金属的闪蒸层。

公开(公告)号：US20130307153A1

公开(公告)日：2013-11-21

申请号：US13474944

申请日：2012-05-18

申请人： Daniel C. Edelstein ,  Takeshi Nogami

发明人： Daniel C. Edelstein ,  Takeshi Nogami

IPC分类号： H01L23/482

CPC分类号： H01L23/53209 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure located on a semiconductor substrate within a dielectric material positioned atop the semiconductor substrate is provided having an opening within the dielectric material, the opening includes an electrically conductive material extending from the bottom to the top, and contacting the sidewall; a first layer located on the sidewall of the opening, the first layer is made from a material including titanium oxide or titanium silicon oxide; a second layer located between the first layer and the electrically conductive material, the second layer is made from a material selected from the group TiXOb, TiXSiaOb, XOb, and XSiaOb, X is Mn, Al, Sn, In, or Zr; and a third layer located along a top surface of the electrically conductive material, the third layer is made from a material selected from the group TiXOb, TiXSiaOb, XOb, and XSiaOb, X is Mn, Al, Sn, In, or Zr.

摘要翻译： 设置在位于半导体衬底顶部的介电材料内的半导体衬底上的互连结构，其具有在电介质材料内的开口，该开口包括从底部延伸到顶部并与侧壁接触的导电材料; 位于所述开口的侧壁上的第一层，所述第一层由包括氧化钛或氧化钛钛的材料制成; 位于第一层和导电材料之间的第二层，第二层由选自TiXOb，TiXSiaOb，XOb和XSiaOb的材料制成，X是Mn，Al，Sn，In或Zr; 以及沿着导电材料的顶表面设置的第三层，第三层由选自TiXOb，TiXSiaOb，XOb和XSiaOb的材料制成，X是Mn，Al，Sn，In或Zr。

公开(公告)号：US08497202B1

公开(公告)日：2013-07-30

申请号：US13400610

申请日：2012-02-21

申请人： Daniel C. Edelstein ,  Takeshi Nogami

发明人： Daniel C. Edelstein ,  Takeshi Nogami

IPC分类号： H01L21/4763

CPC分类号： H01L21/76841 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal.

公开(公告)号：US20130075908A1

公开(公告)日：2013-03-28

申请号：US13246904

申请日：2011-09-28

申请人： Cyril Cabral, JR. ,  Geraud Jean-Michel Dubois ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Daniel P. Sanders

发明人： Cyril Cabral, JR. ,  Geraud Jean-Michel Dubois ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Daniel P. Sanders

IPC分类号： H01L23/482 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

摘要翻译： 公开了一种用于制造具有增强的性能和可靠性的互连结构的互连结构和方法，通过最小化氧侵入种子层和互连结构的电镀铜层。 形成电介质层中的至少一个开口。 形成设置在电介质层上的牺牲氧化层。 牺牲氧化层使氧侵入种子层和互连结构的电镀铜层最小化。 形成设置在牺牲氧化层上的阻挡金属层。 形成设置在阻挡金属层上的籽晶层。 形成设置在种子层上的电镀铜层。 形成平坦化表面，其中除去部分牺牲氧化层，阻挡金属层，种子层和电镀铜层。 此外，形成设置在平坦化表面上的覆盖层。