Method of resource arbitration
    2.
    发明授权
    Method of resource arbitration 失效
    资源仲裁方法

    公开(公告)号:US07099975B2

    公开(公告)日:2006-08-29

    申请号:US10730952

    申请日:2003-12-09

    IPC分类号: G06F12/00

    CPC分类号: G06F13/3625

    摘要: An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

    摘要翻译: 一种改进的资源仲裁方法和装置。 定义了四个优先级,管理高(MH),管理低(ML),机会高(OH)和机会主义低(OL)。 优先级分配给每个资源访问请求。 为每个资源创建访问请求集中器(ARC),通过该资源访问资源。 在优先级顺序为MH,ML,OH和OL的每个ARC中选择访问请求。 如果OH优先级资源访问请求被锁定,优先级顺序将按照优先级的降序暂时更改为OH,OL,MH和ML。 如果OL优先级资源访问请求被锁定,优先级顺序将按照优先级的降序临时更改为MH,OL,OH和ML。

    Methods and apparatus for reducing command processing latency while maintaining coherence
    3.
    发明授权
    Methods and apparatus for reducing command processing latency while maintaining coherence 失效
    减少命令处理延迟同时保持一致性的方法和装置

    公开(公告)号:US08112590B2

    公开(公告)日:2012-02-07

    申请号:US11846697

    申请日:2007-08-29

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    CPC分类号: G06F12/0804 G06F12/0831

    摘要: In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.

    摘要翻译: 在第一方面,提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。 第一种方法包括以下步骤:(1)提供包括可用于系统的存储器地址的存储器映射; 和(2)将存储器地址排列成多个组。 响应于需要访问来自总线单元的组中的存储器地址的命令,组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。 提供了许多其他方面。

    Directory for multi-node coherent bus
    7.
    发明授权
    Directory for multi-node coherent bus 有权
    多节点相干总线目录

    公开(公告)号:US07725660B2

    公开(公告)日:2010-05-25

    申请号:US11828448

    申请日:2007-07-26

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0822

    摘要: A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.

    摘要翻译: 一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。 本地节点确定请求是本地还是系统请求。 如果请求是本地请求,则执行本地节点中的目录的查找。 如果本地节点目录中的条目指示请求中的数据不具有远程所有者,并且请求没有远程目标,则在本地节点上解析数据的一致性,并且传输 如果需要,请求中指定的数据将被执行,并且请求是本地请求。 如果条目指示数据具有远程所有者或请求具有远程目标,则将请求转发到多节点系统中的所有远程节点。

    System and method for flexible multiple protocols
    8.
    发明授权
    System and method for flexible multiple protocols 有权
    灵活多协议的系统和方法

    公开(公告)号:US07647433B2

    公开(公告)日:2010-01-12

    申请号:US11844336

    申请日:2007-08-23

    IPC分类号: G06F3/00

    CPC分类号: G06F13/385

    摘要: A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.

    摘要翻译: 介绍了灵活多协议的系统和方法。 可以在每个接口的基础上动态地配置设备的逻辑层,以以相干或非相干模式与外部设备进行通信。 在相干模式下,诸如一致性协议,系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备,从而创建设备内部系统总线的逻辑扩展。 在非相干模式下,输入 - 输出总线单元从内部系统总线接收命令,并产生最终由外部设备接收的非相干输入 - 输出命令。

    Method and apparatus for implementing data mapping with shuffle algorithm
    9.
    发明授权
    Method and apparatus for implementing data mapping with shuffle algorithm 失效
    用随机播放算法实现数据映射的方法和装置

    公开(公告)号:US07174398B2

    公开(公告)日:2007-02-06

    申请号:US10607360

    申请日:2003-06-26

    IPC分类号: G06F13/00 G06F13/12 G06F15/16

    摘要: A method and apparatus are provided for implementing data mapping using a shuffle algorithm. An output shuffler and an input shuffler convert a physical data group to a plurality of data subgroups. The physical data group includes a plurality of bits and each subgroup includes a subplurality of bits. The output shuffler performs an output shuffle sequence for providing a predefined output pattern of ordered subplurality data bits. The predefined output pattern of ordered subplurality data bits is applied to the input shuffler. The input shuffler performs a reverse shuffle sequence. For each shuffle transfer a number of first header bytes of a packet are located at a first one of a plurality of physical layer links. Both the output shuffler and the input shuffler are implemented with minimized logic required to keep a largest multiplexer as a 4-to-1 multiplexer, resulting in minimal area and power being used for implementing the shuffle sequence and reverse shuffle sequence.

    摘要翻译: 提供了一种使用洗牌算法实现数据映射的方法和装置。 输出洗牌器和输入洗牌器将物理数据组转换为多个数据子组。 物理数据组包括多个比特,并且每个子组包括子层的比特。 输出洗牌器执行输出随机序列,用于提供有序子层数据位的预定义输出模式。 有序副本数据位的预定义输出模式被应用于输入洗牌器。 输入洗牌器执行反向随机序列。 对于每个随机转移,分组的多个第一标题字节位于多个物理层链接中的第一个。 输出洗牌器和输入洗牌器都以最小化的逻辑实现,将最大的复用器保持为4对1多路复用器所需的最小化逻辑,导致用于实现洗牌序列和反相随机序列的最小面积和功率。