公开(公告)号：US5712653A

公开(公告)日：1998-01-27

申请号：US363217

申请日：1994-12-23

申请人： Kenichi Katoh ,  Yasushi Kubota ,  Hiroshi Yoneda ,  Tamotsu Sakai

发明人： Kenichi Katoh ,  Yasushi Kubota ,  Hiroshi Yoneda ,  Tamotsu Sakai

IPC分类号： G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0297 ,  G09G2330/08 ,  G09G3/2011

摘要： An active-matrix image display device which includes n shift registers, analog switches for sampling video input signals and a data-signal-line driving circuit to which n series of clock signals and n.times.m series of video input signals are input, and controls the analog switches according to the result of a logic operation of output pulses from successive l stages in the shift registers. A scanning circuit without using shift registers. Here, n is an integer not smaller than one, m and l are integers not smaller than two. With the image display device, sampling of video signals is surely executed without increasing the number of shift registers. It is thus possible to reduce the size and weight of the image display device and to decrease the defect rate thereof. Moreover, the scanning circuit achieves a higher yield compared with a conventional scanning circuit using a shift register.

公开(公告)号：US6064364A

公开(公告)日：2000-05-16

申请号：US954177

申请日：1997-10-20

申请人： Kenichi Katoh ,  Yasushi Kubota ,  Hiroshi Yoneda ,  Tamotsu Sakai

发明人： Kenichi Katoh ,  Yasushi Kubota ,  Hiroshi Yoneda ,  Tamotsu Sakai

IPC分类号： G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0297 ,  G09G2330/08 ,  G09G3/2011

摘要： An active-matrix image display device which includes n shift registers, analog switches for sampling video input signals and a data-signal-line driving circuit to which n series of clock signals and n.times.m series of video input signals are input, and controls the analog switches according to the result of a logic operation of output pulses from successive l stages in the shift registers. A scanning circuit without using shift registers. Here, n is an integer not smaller than one, m and l are integers not smaller than two. With the image display device, sampling of video signals is surely executed without increasing the number of shift registers. It is thus possible to reduce the size and weight of the image display device and to decrease the defect rate thereof. Moreover, the scanning circuit achieves a higher yield compared with a conventional scanning circuit using a shift register.

摘要翻译： 一种有源矩阵图像显示装置，其包括n个移位寄存器，用于对视频输入信号进行采样的模拟开关和输入n个系列时钟信号和nxm系列视频输入信号的数据信号线驱动电路，并且控制模拟 根据移位寄存器中连续l级的输出脉冲的逻辑运算结果开关。 不使用移位寄存器的扫描电路。 这里，n是不小于1的整数，m和l是不小于2的整数。 利用图像显示装置，可以可靠地执行视频信号的采样而不增加移位寄存器的数量。 因此，可以减小图像显示装置的尺寸和重量并降低其缺陷率。 此外，与使用移位寄存器的常规扫描电路相比，扫描电路实现了更高的产量。

公开(公告)号：US5892495A

公开(公告)日：1999-04-06

申请号：US725314

申请日：1996-10-02

申请人： Tamotsu Sakai ,  Kenichi Katoh ,  Yasushi Kubota

发明人： Tamotsu Sakai ,  Kenichi Katoh ,  Yasushi Kubota

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/06 ,  G09G3/3648

摘要： A scanning circuit is provided with a plurality of address lines and AND circuits. The address lines respectively supply bit signals constituting an address signal and inverted bit signals, and each AND circuit conducts a logical operation on a predetermined number of bit signals and inverted bit signals selected from the bit signals and inverted bit signals supplied from the address lines. The AND circuits are connected to the address lines so that only one bit is switched when the address signal carries. Furthermore, a frequency of the least significant bit of the address signal is set to 1/4 of the dot frequency, while the two bits at the high end are set to have the same frequency and a phase difference of 90.degree. each other. With the described arrangement, a phase shift is prevented from occurring to an outputted signal when the address signal carries. Furthermore, the arrangement ensures that the scanning circuit can be realized in a simple circuit arrangement and operates at low frequencies, thereby ensuring a decrease in power consumption.

摘要翻译： 扫描电路设有多个地址线和“与”电路。 地址线分别提供构成地址信号和反相位信号的位信号，并且每个AND电路根据从地址线提供的位信号和反转位信号中选择的预定数量的位信号和反相位信号进行逻辑运算。 AND电路连接到地址线，使得只有一个位在地址信号传输时被切换。 此外，地址信号的最低有效位的频率被设置为点频的+ E，fra 1/4 + EE，而高端的两位被设置为具有相同的频率和相位差 90°对方。 利用所述的布置，当地址信号携带时，防止对输出信号发生相移。 此外，该布置确保了扫描电路可以以简单的电路布置实现并且在低频下操作，从而确保功耗的降低。

公开(公告)号：US5990857A

公开(公告)日：1999-11-23

申请号：US841585

申请日：1997-04-30

申请人： Yasushi Kubota ,  Kenichi Katoh ,  Jun Koyama ,  Hidehiko Chimura ,  Yukio Tanaka

发明人： Yasushi Kubota ,  Kenichi Katoh ,  Jun Koyama ,  Hidehiko Chimura ,  Yukio Tanaka

IPC分类号： G09G3/20 ,  G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3685 ,  G09G3/3648 ,  G09G3/3666 ,  G09G2310/0286 ,  G09G2330/021

摘要： The shift register of this invention for sequentially transferring a digital signal in synchronization with a clock signal includes: a plurality of circuit blocks connected in series, each including a prescribed number of sequential latch circuits, each latch circuit outputting a signal corresponding to an input signal based on the clock signal; and a plurality of clock signal control circuits provided for the respective circuit blocks for controlling the supply of the clock signal to the latch circuits in the corresponding circuit blocks, wherein the control of the supply of the clock signal by each clock signal control circuit to the latch circuits in the corresponding circuit block is conducted in response to output signals from prescribed latch circuits in the circuit blocks preceding and subsequent to the corresponding circuit block.

摘要翻译： 本发明的用于与时钟信号同步地顺序传送数字信号的移位寄存器包括：串联连接的多个电路块，每个电路块包括规定数量的顺序锁存电路，每个锁存电路输出对应于输入信号的信号 基于时钟信号; 以及多个时钟信号控制电路，用于各个电路块，用于控制向对应的电路块中的锁存电路提供时钟信号，其中控制由每个时钟信号控制电路将时钟信号提供给 响应于相应电路块之前和之后的电路块中来自规定的锁存电路的输出信号，进行相应电路块中的锁存电路。

公开(公告)号：US5926158A

公开(公告)日：1999-07-20

申请号：US610128

申请日：1996-02-29

申请人： Hiroshi Yoneda ,  Kenichi Katoh ,  Yutaka Ishii ,  Yasushi Kubota

发明人： Hiroshi Yoneda ,  Kenichi Katoh ,  Yutaka Ishii ,  Yasushi Kubota

IPC分类号： G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3659 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G2330/023 ,  G09G3/2011

摘要： An active matrix type image display apparatus which includes: a plurality of data signal lines; a plurality of scanning signal lines crossing the plurality of data signal lines; and a plurality of pixel portions disposed in a matrix in areas enclosed by the plurality of data signal lines and the plurality of scanning signal lines, wherein each of the plurality of pixel portions includes: a pixel capacitor for storing electric charge supplied from at least one of the plurality of data signal lines, to display an image; storage unit connected to the pixel capacitor; and switching unit which alternately selects one of an operation for electrically connecting the pixel capacitor to the storage unit and an operation for electrically disconnecting the pixel capacitor from the storage unit.

摘要翻译： 一种有源矩阵型图像显示装置，包括：多条数据信号线; 与所述多条数据信号线交叉的多条扫描信号线; 以及由多个数据信号线和多条扫描信号线包围的区域中矩阵地配置的多个像素部，其中，所述多个像素部分中的每一个包括：像素电容器，用于存储从至少一个 的多个数据信号线，以显示图像; 存储单元连接到像素电容器; 以及切换单元，其交替地选择用于将像素电容器电连接到存储单元的操作中的一个以及用于将像素电容器与存储单元电气断开的操作。

公开(公告)号：US6011535A

公开(公告)日：2000-01-04

申请号：US744054

申请日：1996-11-05

申请人： Kenichi Katoh ,  Yasushi Kubota ,  Hidehiko Chimura ,  Jun Koyama

发明人： Kenichi Katoh ,  Yasushi Kubota ,  Hidehiko Chimura ,  Jun Koyama

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0283

摘要： A scanning circuit for a display device having an array of pixels. One embodiment of the scanning circuit includes L scan control signal lines, first logic circuits to operate on signals from M of the L scan control signal lines, flip-flop circuits communicating with the first logic circuits, N timing control signal lines, and second logic circuits coupled to operate on signal from the N timing control signal lines and the flip-flop circuits.

摘要翻译： 一种具有像素阵列的显示装置的扫描电路。 扫描电路的一个实施例包括L扫描控制信号线，对来自L扫描控制信号线的M的信号进行操作的第一逻辑电路，与第一逻辑电路通信的触发电路，N个定时控制信号线和第二逻辑 耦合到来自N个定时控制信号线和触发器电路的信号的电路。

公开(公告)号：US5734366A

公开(公告)日：1998-03-31

申请号：US554286

申请日：1995-11-06

申请人： Yasushi Kubota ,  Kenichi Katoh ,  Hiroshi Yoneda

发明人： Yasushi Kubota ,  Kenichi Katoh ,  Hiroshi Yoneda

IPC分类号： G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  H03F1/30 ,  H03G1/00 ,  H04N5/14 ,  H04N5/16 ,  H04N5/66 ,  H04N5/68 ,  H04N5/70

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G11C19/00 ,  H03F1/303 ,  H03G1/00 ,  H04N5/68 ,  H04N5/148 ,  H04N5/16 ,  H04N5/66 ,  H04N5/70

摘要： An image display device includes an operational amplifier, a signal amplifier provided with a condenser for setting a gain of the operational amplifier, a signal amplifier circuit having such signal amplifier or a buffer amplifier, the signal amplifier circuit being provided with an offset adjusting function, and a data signal line drive circuit having a signal amplifier or a signal line drive circuit. The described arrangement enables the gain of the signal amplifier to be set by a capacitance of the condenser, thereby providing a signal amplifier circuit which permits the gain to be set much more precisely as compared to the conventional signal amplifier circuits even when adopting a signal amplifier formed on a semiconductor thin film such as a polycrystalline silicone thin film. The arrangement also provides a signal amplifier circuit which permits a voltage in the same level as a voltage of the input signal to be outputted. Furthermore, the arrangement provides high quality data signal line drive circuit and the image display device.

公开(公告)号：US06448954B1

公开(公告)日：2002-09-10

申请号：US09420893

申请日：1999-10-19

申请人： Kenichi Katoh ,  Yasushi Kubota ,  Hidehiko Chimura ,  Jun Koyama

发明人： Kenichi Katoh ,  Yasushi Kubota ,  Hidehiko Chimura ,  Jun Koyama

IPC分类号： G09G336

CPC分类号： G09G3/3677 ,  G09G2310/0283

摘要： An active matrix display device has a number of pixels arranged in matrix form, signal lines for supplying display signals to the pixels, and a driver circuit for driving the signal lines. The driver circuit includes a frequency divider circuit for frequency-dividing input multi-phase clock signals, a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals, and a decoder circuit for selecting a desired one of the signal lines based on outputs of the frequency divider circuit and the synchronous counter circuit.

摘要翻译： 有源矩阵显示装置具有以矩阵形式布置的多个像素，用于向像素提供显示信号的信号线以及用于驱动信号线的驱动电路。 驱动器电路包括用于对输入多相时钟信号进行分频的分频器电路，用于对输入多相时钟信号的一部分进行分频的同步计数器电路和用于选择所需信号线的解码器电路 基于分频器电路和同步计数器电路的输出。

公开(公告)号：US5977944A

公开(公告)日：1999-11-02

申请号：US909481

申请日：1997-08-11

申请人： Yasushi Kubota ,  Kenichi Katoh ,  Ichiro Shiraki

发明人： Yasushi Kubota ,  Kenichi Katoh ,  Ichiro Shiraki

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  H03K17/00

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/2074

摘要： A data signal output circuit is divided into a plurality of blocks, each having its own supply circuit. In each block, a plurality of shift register sections, constituting a shift register, output pulse signals which have been shifted according to clock signals. Driving sections sample a digital image signal in synchronism with the pulse signal, and output data signals corresponding to the image signal thus sampled to a plurality of output lines. Each supply circuit provided in the blocks receives the image signal when the image signal should be sampled by the driving sections, thereby supplying the image signal only to the minimum number of blocks to be operated. In this manner, the image signal is selectively supplied to the block so as to reduce the effective load on the image signal. As a result, the power consumption generated in the image signal lines can be reduced.

摘要翻译： 数据信号输出电路被分成多个块，每个块具有其自己的供电电路。 在每个块中，构成移位寄存器的多个移位寄存器部分输出根据时钟信号被移位的脉冲信号。 驱动部分与脉冲信号同步地采样数字图像信号，并且将与所采样的图像信号对应的数据信号输出到多条输出线。 当图像信号被驱动部分采样时，在块中提供的每个供给电路接收图像信号，从而仅将图像信号提供给要被操作的最小数量的块。 以这种方式，图像信号被选择性地提供给块，以便减小对图像信号的有效负载。 结果，可以减少图像信号线中产生的功率消耗。

公开(公告)号：US5926156A

公开(公告)日：1999-07-20

申请号：US556140

申请日：1995-11-09

申请人： Kenichi Katoh ,  Yasushi Kubota ,  Hiroshi Yoneda ,  Osamu Sasaki ,  Ichiro Shiraki

发明人： Kenichi Katoh ,  Yasushi Kubota ,  Hiroshi Yoneda ,  Osamu Sasaki ,  Ichiro Shiraki

IPC分类号： G09G3/36 ,  G02F1/136

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2330/08

摘要： A driving circuit in a matrix type image display apparatus including a plurality of groups each including four standard unit circuits and one backup unit circuit. Each standard unit circuit includes disconnecting means for isolating the standard unit circuit from the driving circuit, and the backup unit circuit includes connecting means for connecting the backup unit circuit to an input signal line and an output signal line of any of the standard unit circuits within a group. The number of the backup unit circuits can be changed in accordance with a conforming ratio of each unit circuit, which makes it possible to eliminate idle backup unit circuits while maintaining a high overall conforming ratio of the driving circuit, thereby enhancing manufacturing efficiencies and reducing manufacturing costs.

摘要翻译： 一种矩阵型图像显示装置中的驱动电路，包括多个组，每组包括四个标准单元电路和一个备用单元电路。 每个标准单元电路包括用于将标准单元电路与驱动电路隔离的断开装置，并且备用单元电路包括用于将备用单元电路连接到任何标准单元电路的输入信号线和输出信号线的连接装置 一个小组。 备用单元电路的数量可以根据每个单元电路的一致比例而改变，这使得可以在保持驱动电路的高整体比例的同时消除空闲备用单元电路，从而提高制造效率并减少制造 费用