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    Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance
    1.
    发明授权
    Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
    一种用于使用具有可调整电阻的可切换半导体存储元件的存储单元的方法

    公开(公告)号：US07800933B2

    公开(公告)日：2010-09-21

    申请号：US11496986

    申请日：2006-07-31

    申请人： Tanmay Kumar ,  S. Brad Herner ,  Roy E Scheuerlein ,  Christopher J Petti

    发明人： Tanmay Kumar ,  S. Brad Herner ,  Roy E Scheuerlein ,  Christopher J Petti

    IPC分类号： G11C11/00 ,  G11C11/36

    CPC分类号： G11C11/5692 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/165 ,  G11C2013/0073 ,  H01L27/101

    摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.

    摘要翻译： 包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲 二极管在正向偏置下，而复位脉冲以二极管反向施加。 通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。

    NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL
    2.
    发明申请
    NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL 有权
    包含二极管和电阻切换材料的非易失性存储单元

    公开(公告)号：US20100302836A1

    公开(公告)日：2010-12-02

    申请号：US12855462

    申请日：2010-08-12

    申请人： S. Brad Herner ,  Tanmay Kumar ,  Christopher J. Petti

    发明人： S. Brad Herner ,  Tanmay Kumar ,  Christopher J. Petti

    IPC分类号： G11C11/00 ,  H01L21/16

    CPC分类号： H01L27/249 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

    摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.

    摘要翻译： 在形成于衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NixOy，NbxOy，TixOy，HfxOy，AlxOy，MgxOy，CoxOy，CrxOy ，VxOy，ZnxOy，ZrxOy，BxNy和AlxNy。 在优选实施例中，二极管形成为设置在导体之间的垂直支柱。 可以堆叠多个存储器级别以形成单片三维存储器阵列。 在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。 本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

    Nonvolatile memory cell comprising a diode and a resistance-switching material
    4.
    发明授权
    Nonvolatile memory cell comprising a diode and a resistance-switching material 有权
    包括二极管和电阻切换材料的非易失性存储单元

    公开(公告)号：US07812404B2

    公开(公告)日：2010-10-12

    申请号：US11395995

    申请日：2006-03-31

    申请人： S. Brad Herner ,  Tanmay Kumar ,  Christopher J. Petti

    发明人： S. Brad Herner ,  Tanmay Kumar ,  Christopher J. Petti

    IPC分类号： H01L29/76

    CPC分类号： H01L27/249 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

    摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HFxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.

    摘要翻译： 在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NixOy，NbxOy，TixOy，HFxOy，AlxOy，MgxOy，CoxOy，CrxOy ，VxOy，ZnxOy，ZrxOy，BxNy和AlxNy。 在优选实施例中，二极管形成为设置在导体之间的垂直支柱。 可以堆叠多个存储器级别以形成单片三维存储器阵列。 在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。 本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

    Transistor layout configuration for tight-pitched memory array lines
    5.
    发明授权
    Transistor layout configuration for tight-pitched memory array lines 有权
    紧凑型内存阵列线的晶体管布局配置

    公开(公告)号：US07177227B2

    公开(公告)日：2007-02-13

    申请号：US11420787

    申请日：2006-05-29

    申请人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    发明人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    IPC分类号： G11C8/00 ,  G11C7/00

    CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C8/08 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10894 ,  H01L27/10897

    摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.

    摘要翻译： 多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。 在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。 垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。 每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管 线。 在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

    Transistor layout configuration for tight-pitched memory array lines
    6.
    发明授权
    Transistor layout configuration for tight-pitched memory array lines 有权
    紧凑型内存阵列线的晶体管布局配置

    公开(公告)号：US07054219B1

    公开(公告)日：2006-05-30

    申请号：US11095905

    申请日：2005-03-31

    申请人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    发明人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    IPC分类号： G11C8/00

    CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C8/08 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10894 ,  H01L27/10897

    摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.

    摘要翻译： 多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。 在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。 垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。 每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管 线。

    Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
    7.
    发明授权
    Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride 有权
    异质结装置包括半导体和电阻率切换氧化物或氮化物

    公开(公告)号：US08227787B2

    公开(公告)日：2012-07-24

    申请号：US13007812

    申请日：2011-01-17

    申请人： Tanmay Kumar ,  S. Brad Herner

    发明人： Tanmay Kumar ,  S. Brad Herner

    IPC分类号： H01L29/02 ,  H01L47/00

    CPC分类号： H01L29/868 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/165 ,  H01L29/22 ,  H01L29/267 ,  H01L29/417 ,  H01L29/737 ,  H01L29/8615 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

    摘要： In the present invention, a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor. For example, a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.

    摘要翻译： 在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。 该p-n异质结可以用于各种装置中。 在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成。 例如，二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。 这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。

    Memory cell comprising switchable semiconductor memory element with trimmable resistance
    9.
    发明授权
    Memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
    存储单元包括具有可调整电阻的可切换半导体存储元件

    公开(公告)号：US07800932B2

    公开(公告)日：2010-09-21

    申请号：US11237167

    申请日：2005-09-28

    申请人： Tanmay Kumar ,  S. Brad Herner

    发明人： Tanmay Kumar ,  S. Brad Herner

    IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15

    CPC分类号： G11C11/5692 ,  G11C11/005 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C17/14 ,  G11C2211/5641 ,  G11C2211/5646 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/148

    摘要： A nonvolatile memory cell comprising doped semiconductor material and a diode can store memory states by changing the resistance of the doped semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) Set pulses are of short duration and above a threshold voltage, while reset pulses are longer duration and below a threshold voltage. In some embodiments multiple resistance states can be achieved, allowing for a multi-state cell, while restoring a prior high-resistance state allows for an rewriteable cell. In some embodiments, the diode and a switchable memory formed of doped semiconductor material are formed in series, while in other embodiments, the diode itself serves as the semiconductor switchable memory element.

    摘要翻译： 包括掺杂半导体材料和二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变掺杂半导体材料的电阻来存储存储器状态。设置脉冲的持续时间短， 高于阈值电压，而复位脉冲的持续时间更长并低于阈值电压。 在一些实施例中，可以实现多个电阻状态，允许多状态单元，同时恢复先前的高电阻状态允许可重写单元。 在一些实施例中，二极管和由掺杂半导体材料形成的可切换存储器是串联形成的，而在其它实施例中，二极管本身用作半导体可切换存储元件。