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13 条记录 (耗时 0.022 秒)

    Method and device for pulse density modulation
    1.
    发明授权
    Method and device for pulse density modulation 有权

    公开(公告)号：US06563393B2

    公开(公告)日：2003-05-13

    申请号：US09961884

    申请日：2001-09-24

    申请人： Tao Zhang ,  Hiroshi Katsuragawa ,  Noriyoshi Ito

    发明人： Tao Zhang ,  Hiroshi Katsuragawa ,  Noriyoshi Ito

    IPC分类号： H03C300

    CPC分类号： H03M7/00

    摘要： A pulse density modulator unit transforms an N-bit input signal representing an input value, into an output digital signal having a digital pulse density which is a linear function of the input value. The pulse density modulator unit includes a first pulse density modulator which produces a binary signal representing a multiplication factor as a pulse density. It further includes a combination module which receives the input signal, the binary signal from the first pulse density modulator and an offset control signal. The combination module produces a combined signal which, on average, represents the product of the input signal and the amplification control signal, offset by an amount dependent upon the offset control signal. A second pulse generator uses the combined signal to generate the output digital signal. The combination module may be a selector.

    Recursive decoder for switching between normalized and non-normalized probability estimates
    2.
    发明授权
    Recursive decoder for switching between normalized and non-normalized probability estimates 有权
    用于在归一化和非归一化概率估计之间切换的递归解码器

    公开(公告)号：US07120851B2

    公开(公告)日：2006-10-10

    申请号：US10649785

    申请日：2003-08-28

    申请人： Yu Jing Ting ,  Noriyoshi Ito ,  Hiroshi Katsuragawa

    发明人： Yu Jing Ting ,  Noriyoshi Ito ,  Hiroshi Katsuragawa

    IPC分类号： H03M13/00 ,  H03M13/03

    CPC分类号： H03M13/3927 ,  H03M13/2978

    摘要： The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.

    摘要翻译： 本发明一般涉及纠错编码，更具体地说，涉及用于级联码（例如，turbo码）的解码器。 本发明提供了一种用于对编码数据进行解码的解码器，该解码器包括：一个处理器，具有一个输入，该输入接收一个符号块的概率估计，并且被配置为在下一个迭代状态下计算所述符号的概率估计; 规范化所述下一状态估计的正规化装置; 接收所述归一化和所述非标准化下一状态估计的开关，所述开关的输出耦合到所述处理器的输入; 其中所述开关被布置为根据迭代状态在归一化和非标准化的下一状态估计之间切换。

    CDMA receiver
    3.
    发明授权
    CDMA receiver 失效
    CDMA接收机

    公开(公告)号：US06266365B1

    公开(公告)日：2001-07-24

    申请号：US09572625

    申请日：2000-05-17

    申请人： Zhaocheng Wang ,  Tao Zhang ,  Noriyoshi Ito ,  Hiroki Sugimoto

    发明人： Zhaocheng Wang ,  Tao Zhang ,  Noriyoshi Ito ,  Hiroki Sugimoto

    IPC分类号： A61F206

    CPC分类号： H04B1/7085 ,  H04B1/709

    摘要： A code division multiple access (CDMA) receiver for receiving an encoded CDMA signal is disclosed, the receiver comprising an analog to digital converter for sampling a received signal and passing the thus sampled and digitized signal to a CDMA decoder, the converter receiving a sampling clock signal at a sampling frequency, the phase of the clock signal being adjustable. The CDMA decoder includes a plurality of sets of correlators, each set having a different base delay, each base delay being adjustable.

    摘要翻译： 公开了一种用于接收编码的CDMA信号的码分多址（CDMA）接收机，该接收机包括一个模数转换器，用于对接收到的信号进行采样，并将这样采样和数字化的信号传送到CDMA解码器，该转换器接收采样时钟 信号采样频率，时钟信号的相位可调。 CDMA解码器包括多组相关器，每组相关器具有不同的基极延迟，每个基极延迟是可调节的。

    Sample clock extracting circuit and baseband signal receiving circuit
    4.
    发明授权
    Sample clock extracting circuit and baseband signal receiving circuit 失效
    采样时钟提取电路和基带信号接收电路

    公开(公告)号：US07151812B2

    公开(公告)日：2006-12-19

    申请号：US10254643

    申请日：2002-09-26

    申请人： Noriyoshi Ito

    发明人： Noriyoshi Ito

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337 ,  H04L7/042

    摘要： A sample clock extracting circuit comprises including a number-of-change point memory, a number-of-change point updating circuit and an output clock phase determining circuit. The number-of-change point memory stores a number-of-change-point information set every N types of clock phases each having a frequency equivalent to N times a symbol transmission rate of an input baseband signal. The number-of-change point updating circuit updates the number-of-change point information stored in the number-of-change point memory about a clock phase related to timing thereof when a rising change point or a falling change point occurs in the baseband signal. The output clock phase determining circuit determines a clock phase directly or indirectly indicative of a sample clock phase for the baseband signal based on the number-of-change-point information stored in the number-of-change point memory.

    摘要翻译： 一个采样时钟提取电路包括一个变化点数存储器，一个变化点数更新电路和一个输出时钟相位确定电路。 变化点数存储器存储每N个时钟相位的变化点数信息，每个时钟相位具有等于输入基带信号的符号传输速率的N倍的频率。 改变点数更新电路在基带中发生上升变化点或下降变化点时，更新存储在变化数量点存储器中的与其定时有关的时钟相位的变化数量点信息 信号。 输出时钟相位确定电路基于存储在变化点数存储器中的变化数量信息，直接或间接地确定基带信号的采样时钟相位的时钟相位。

    Rotary slide bearing and producing method therefor
    5.
    发明授权
    Rotary slide bearing and producing method therefor 失效
    旋转滑动轴承及其制造方法

    公开(公告)号：US06176621B1

    公开(公告)日：2001-01-23

    申请号：US09109080

    申请日：1998-07-02

    申请人： Hiroshi Naitoh ,  Arihiro Kimura ,  Koji Kuroda ,  Hiroshi Murakami ,  Noriyoshi Ito ,  Tadashi Tanaka

    发明人： Hiroshi Naitoh ,  Arihiro Kimura ,  Koji Kuroda ,  Hiroshi Murakami ,  Noriyoshi Ito ,  Tadashi Tanaka

    IPC分类号： F16C3310

    CPC分类号： F16C33/14 ,  F16C9/00 ,  F16C17/022 ,  F16C33/1065

    摘要： A rotary slide bearing part of a rotary slide slit bearing for supporting a rotary shaft thereon in a rotatable manner, has a first bearing surface portion adapted to be arranged adjacent to a second bearing surface portion of another rotary slide bearing part of the rotary slide slit bearing, a load from the shaft to be borne by the first bearing surface portion is larger than a load from the shaft to be borne by the second bearing surface portion, the first bearing surface portion includes a fluidal pressure generating surface facing close to the shaft to generate a fluidal pressure between the fluidal pressure generating surface and the shaft, a main groove arranged at an circumferential end of the first bearing surface portion adjacent to the second bearing surface portion, and a sub-groove extending from the main groove in a circumferential direction of the first bearing surface portion, and an axial width of the sub-groove is smaller than that of the main groove.

    摘要翻译： 用于以可旋转的方式支撑旋转轴的旋转滑动狭缝轴承的旋转滑动轴承部分具有适于邻近旋转滑动狭缝的另一旋转滑动轴承部分的第二支承表面部分布置的第一轴承表面部分 由第一轴承面部承载的来自轴的负荷大于由第二轴承面部承受的来自轴的负荷，第一轴承面部包括面对靠近轴的流体压力生成面 在所述流体压力产生表面和所述轴之间产生流体压力，布置在所述第一支承表面部分的与所述第二支承表面部分相邻的圆周端处的主凹槽以及从所述主凹槽沿周向延伸的副凹槽 第一支承面部的方向，副槽的轴向宽度小于主槽的轴向宽度。

    Hard/soft cooperative verifying simulator
    6.
    发明授权
    Hard/soft cooperative verifying simulator 失效
    硬/软协同验证模拟器

    公开(公告)号：US07957950B2

    公开(公告)日：2011-06-07

    申请号：US12039005

    申请日：2008-02-28

    申请人： Noriyoshi Ito

    发明人： Noriyoshi Ito

    IPC分类号： G06G7/62 ,  G06F17/50

    CPC分类号： G06F17/5022

    摘要： A hard/soft cooperative verifying simulator is based on a SystemC simulator, and provides the capability of reducing overhead of context switching control thereby to shorten processing time. Time keepers for controlling simulation times of a plurality of threads are provided corresponding to the threads generated as simulation models for hardware and software. Each of the time keepers has a variable which holds a simulation time for each thread, a variable which holds a summation time, and a break request queue which stores a break time and its corresponding break method therein. The time keeper manages both variables and the queue in response to six types of method invocations from the thread, and invokes a wait function of the SystemC simulator when necessary. It is thus possible to reduce the number of times that a wait function invocation is performed, and shorten the entire processing time.

    摘要翻译： 硬/软协作验证模拟器基于SystemC模拟器，并且提供减少上下文切换控制的开销的能力，从而缩短处理时间。 对应于作为硬件和软件的仿真模型生成的线程，提供用于控制多个线程的仿真时间的时间控制器。 每个时间守护者都有一个变量，它保存每个线程的模拟时间，一个保存求和时间的变量，以及一个在其中存储中断时间及其相应的中断方法的中断请求队列。 时间守护者根据线程的六种类型的方法调用来管理变量和队列，并在必要时调用SystemC模拟器的等待功能。 因此可以减少执行等待功能调用的次数，并缩短整个处理时间。

    Card for bingo game type dice game
    8.
    发明申请
    Card for bingo game type dice game 审中-公开
    用于宾果游戏类型骰子游戏卡

    公开(公告)号：US20090121430A1

    公开(公告)日：2009-05-14

    申请号：US12149828

    申请日：2008-05-08

    申请人： Noriyoshi Ito

    发明人： Noriyoshi Ito

    IPC分类号： A63F3/06

    CPC分类号： A63F3/0695 ,  A63F3/062 ,  A63F9/04

    摘要： To provide a card for a dice game capable of simply and conveniently enjoying a game substantially similar to a bingo game by using a dice in place of a numeral lottery machine, there is provided a card used in a dice game of a bingo game type using a dice, in which a surface of the card is provided with vertical 4 columns and horizontal 4 rows of boxes, and numerals indicating sums of numerals of pips on dices and pairs of equal numerals which come out when two pieces of dices are cast once or one piece of a dice is cast twice are described in the boxes. Any 4 kinds of the pairs of equal numerals in 6 kinds of pairs of equal numerals of 1 and 1, 2 and 2, 3 and 3, 4 and 4, 5 and 5, and 6 and 6 which come out when the two pieces of dices are cast once or the one piece of dice is cast twice may be aligned to describe in a diagonal line direction of the boxes, and remaining 2 kinds of pairs of equal numerals may be described in the boxes of corner portions on both sides in a diagonal line direction different from the above-described diagonal line direction.

    摘要翻译： 为了提供一种能够通过使用骰子代替数字彩票机简单方便地享受与宾果游戏基本相似的游戏的骰子游戏卡，提供了一种用于宾果游戏类型的骰子游戏中使用的卡片，其使用 一个骰子，其中卡的表面设置有垂直的4列和水平的4行盒，以及表示两个骰子投掷一次时出现的骰子和相同数字对的数字的数字和的数字的数字的数字， 一盒骰子被投了两次，在箱子里描述。 任何4种相同数字的对，分别为1和1,2和2,3和3,4,4,5,5和6和6的相同的数字对，当两个 骰子被铸造一次，或者一片骰子被铸造两次可以对齐以描述框的对角线方向，并且剩余的两种相等的数字对可以在两侧的角部分框中描述 对角线方向与上述对角线方向不同。

    Syncword detecting circuit and a baseband signal receiving circuit
    10.
    发明申请
    Syncword detecting circuit and a baseband signal receiving circuit 失效
    同步检测电路和基带信号接收电路

    公开(公告)号：US20050163274A1

    公开(公告)日：2005-07-28

    申请号：US11011767

    申请日：2004-12-15

    申请人： Noriyoshi Ito

    发明人： Noriyoshi Ito

    IPC分类号： H04L27/22 ,  H04B7/26 ,  H04L7/00 ,  H04L7/04

    CPC分类号： H04L7/042

    摘要： A predetermined syncword detecting circuit includes a matched-bit-number comparing circuit, a comparing-result-change detecting circuit, a detected-result storing circuit, a total number detecting circuit, and a syncword detecting circuit. The matched-bit-number comparing circuit acquires a number of bits in a baseband signal that matches bits of the predetermined syncword and compares the number with a first threshold. The comparing-result-change detecting circuit samples the result of the matched-bit-number comparing circuit. The comparing-result-change detecting circuit detects changes in the result of the matched-bit-number comparing circuit. The detected-result storing circuit sequentially stores a result of the comparing-result-change detecting circuit. The total-number detecting circuit detects a total number of the result of the matched-bit-number comparing circuit. The result is included in an N cycle period and surpasses the first threshold. The syncword detecting circuit detects the predetermined syncword and selects an intermediate phase of the cycles as a detection phase.

    摘要翻译： 预定的同步字检测电路包括匹配比特数比较电路，比较结果改变检测电路，检测结果存储电路，总数检测电路和同步字检测电路。 匹配位数比较电路获取与预定同步字的比特匹配的基带信号中的比特数，并将该数与第一阈值进行比较。 比较结果变化检测电路对匹配比特数比较电路的结果进行采样。 比较结果变化检测电路检测匹配位数比较电路的结果的变化。 检测结果存储电路依次存储比较结果变化检测电路的结果。 总数检测电路检测匹配比特数比较电路的结果的总数。 结果包含在N周期内，超过第一个阈值。 同步字检测电路检测预定的同步字，并选择周期的中间相作为检测阶段。