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    Capacitor cell, semiconductor device and process for manufacturing the same
    2.
    发明授权
    Capacitor cell, semiconductor device and process for manufacturing the same 有权
    电容器电池，半导体器件及其制造方法

    公开(公告)号：US07161792B2

    公开(公告)日：2007-01-09

    申请号：US10845197

    申请日：2004-05-14

    申请人： Taro Sakurabayashi ,  Toshikazu Kato

    发明人： Taro Sakurabayashi ,  Toshikazu Kato

    IPC分类号： H01G4/005

    CPC分类号： H01L27/0805 ,  H01L27/0207

    摘要： A capacitor cell for reducing noise in a high drive cell includes a plurality of vias for supplying power to an interconnection layer positioned over the capacitor cell from an upper interconnection layer, so that the resistance of the power supply path is reduced.

    摘要翻译： 用于降低高驱动单元中的噪声的电容器单元包括多个通孔，用于从上部互连层向位于电容器单元上的布线层供电，从而减小了电源路径的电阻。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM 有权
    半导体集成电路和电源电压自适应控制系统

    公开(公告)号：US20120182047A1

    公开(公告)日：2012-07-19

    申请号：US13349279

    申请日：2012-01-12

    申请人： Masahiro NOMURA ,  Taro Sakurabayashi

    发明人： Masahiro NOMURA ,  Taro Sakurabayashi

    IPC分类号： H03K3/00 ,  H03K19/21

    CPC分类号： H03K19/1731 ,  G01R31/318575 ,  H03K3/0375 ,  H03K19/0008 ,  H03K19/0016 ,  H03K19/17728 ,  H03K19/1776

    摘要： A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

    摘要翻译： 半导体集成电路具有：N个输入端子; N个输出端子; 多个触发器，包括N个触发器和R个冗余触发器; 选择器部分，被配置为根据重新配置信息从多个触发器中选择N个选择的触发器，并且切换数据流，使得输入到N个输入端的数据通过N个选择的触发器分别输出到N个输出端， 翻牌 和错误检测部。 在测试模式下，N个触发器形成扫描链，扫描数据被输入到扫描链。 误差检测部分在测试模式下，基于在N个触发器中分别输入/输出的扫描输入/输出数据来检测包括在N个触发器中的错误触发器，并进一步产生重新配置信息， N选择的触发器不包括错误触发器。

    Semiconductor device including power switch and power reinforcement cell
    5.
    发明授权
    Semiconductor device including power switch and power reinforcement cell 失效
    半导体器件包括电源开关和电源增强电池

    公开(公告)号：US07768768B2

    公开(公告)日：2010-08-03

    申请号：US12078764

    申请日：2008-04-04

    申请人： Taro Sakurabayashi

    发明人： Taro Sakurabayashi

    IPC分类号： H01L23/58

    CPC分类号： H01L23/5286 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor device according to one embodiment includes a cell disposition region in which plural basic cells are disposed and a basic power supply wiring. In the cell disposition region are disposed a primitive cell connected to the basic power supply wiring and a high current consumption cell connected to the basic power supply wiring. Furthermore, in the cell disposition region are disposed regularly plural ordinary power switch cells that supply a first current to the primitive cell respectively. The power reinforcement cell including a power switch cell configured so as to flow a predetermined current to the high current consumption cell is disposed near the high current consumption cell.

    摘要翻译： 根据一个实施例的半导体器件包括其中设置有多个基本单元的单元布置区域和基本电源布线。 在单元配置区域中设置连接到基本电源布线的原始单元和连接到基本电源布线的大电流消耗单元。 此外，在单元配置区域中规则地设置有分别向原始单元提供第一电流的多个普通电力开关单元。 包括配置为使预定电流流向高电流消耗单元的功率开关单元的功率增强单元设置在高电流消耗单元附近。

    Semiconductor integrated circuit and power-supply voltage adaptive control system
    6.
    发明授权
    Semiconductor integrated circuit and power-supply voltage adaptive control system 有权
    半导体集成电路和电源电压自适应控制系统

    公开(公告)号：US08996940B2

    公开(公告)日：2015-03-31

    申请号：US13349279

    申请日：2012-01-12

    申请人： Masahiro Nomura ,  Taro Sakurabayashi

    发明人： Masahiro Nomura ,  Taro Sakurabayashi

    IPC分类号： G01R31/28 ,  H03K3/037 ,  G01R31/3185 ,  H03K19/00

    CPC分类号： H03K19/1731 ,  G01R31/318575 ,  H03K3/0375 ,  H03K19/0008 ,  H03K19/0016 ,  H03K19/17728 ,  H03K19/1776

    摘要： A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

    摘要翻译： 半导体集成电路具有：N个输入端子; N个输出端子; 多个触发器，包括N个触发器和R个冗余触发器; 选择器部分，被配置为根据重新配置信息从多个触发器中选择N个选择的触发器，并且切换数据流，使得输入到N个输入端的数据通过N个选择的触发器分别输出到N个输出端， 翻牌 和错误检测部。 在测试模式下，N个触发器形成扫描链，扫描数据被输入到扫描链。 误差检测部分在测试模式下，基于在N个触发器中分别输入/输出的扫描输入/输出数据来检测包括在N个触发器中的错误触发器，并进一步产生重新配置信息， N选择的触发器不包括错误触发器。

    Semiconductor integrated circuit device
    7.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20070222082A1

    公开(公告)日：2007-09-27

    申请号：US11723827

    申请日：2007-03-22

    申请人： Hideo Sonohara ,  Taro Sakurabayashi

    发明人： Hideo Sonohara ,  Taro Sakurabayashi

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5286 ,  H01L24/02 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/14

    摘要： A semiconductor integrated circuit device of improved wireability, fewer number of wiring layers and strengthened power supply includes a plurality of power pads placed on a semiconductor chip and a plurality of signal pads placed on the semiconductor chip and configured to have a width less than that of the power pads. The signal pads and the power pads are placed in the uppermost wiring layer among a plurality of wiring layers. Signal wiring connecting I/O cells and signal pads is disposed in the uppermost wiring layer. First power wiring electrically connecting the I/O cells and first power pads is disposed in the uppermost wiring layer. Second power wiring connecting internal circuits and second power pads is disposed in the uppermost wiring layer.

    摘要翻译： 一种改进的可线性，更少的布线层数和强化电源的半导体集成电路器件包括放置在半导体芯片上的多个电源焊盘和放置在半导体芯片上的多个信号焊盘，并且被配置为具有小于 电源垫。 信号焊盘和电源焊盘被放置在多个布线层中的最上层布线层中。 连接I / O单元和信号垫的信号线布置在最上层布线层中。 电连接I / O单元和第一功率垫的第一功率配线布置在最上层布线层中。 连接内部电路和第二电源焊盘的第二电源配线设置在最上层布线层中。

    ARRANGEMENT OF POWER SUPPLY CELLS WITHIN CELL-BASE INTEGRATED CIRCUIT
    8.
    发明申请
    ARRANGEMENT OF POWER SUPPLY CELLS WITHIN CELL-BASE INTEGRATED CIRCUIT 审中-公开
    电池组集成电路中电源电极的布置

    公开(公告)号：US20100308667A1

    公开(公告)日：2010-12-09

    申请号：US12789727

    申请日：2010-05-28

    申请人： Taro Sakurabayashi

    发明人： Taro Sakurabayashi

    IPC分类号： H02B1/20

    CPC分类号： H01L27/11807 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is provided with a first power supply cell, first cells and second cells. The first power supply cell and the first cells are continuously arrayed in a row direction in a first row. The second cells are continuously arrayed in the row direction in a second row adjacent to the first row. The first power supply cell is connected to a first power supply line extending perpendicularly to the row direction to feed a power supply voltage corresponding to a voltage fed from the first power supply line to the plurality of first and second cells. One of the second cells is indirectly connected to the first power supply line through the first power supply cell, the one of the second cells being positioned adjacent to the first power supply cell.

    摘要翻译： 半导体器件设置有第一电源单元，第一单元和第二单元。 第一电源单元和第一单元在第一行中沿行方向连续排列。 在与第一行相邻的第二行中，第二单元在行方向上连续排列。 第一电源单元连接到垂直于行方向延伸的第一电源线，以将与从第一电源线馈送的电压相对应的电源电压馈送到多个第一和第二单元。 第二单元之一通过第一电源单元间接连接到第一电源线，第二单元中的一个位于与第一电源单元相邻的位置。

    Semiconductor integrated circuit device
    9.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07541683B2

    公开(公告)日：2009-06-02

    申请号：US11723827

    申请日：2007-03-22

    申请人： Hideo Sonohara ,  Taro Sakurabayashi

    发明人： Hideo Sonohara ,  Taro Sakurabayashi

    IPC分类号： H01L29/40

    CPC分类号： H01L23/5286 ,  H01L24/02 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/14

    摘要： A semiconductor integrated circuit device of improved wireability, fewer number of wiring layers and strengthened power supply includes a plurality of power pads placed on a semiconductor chip and a plurality of signal pads placed on the semiconductor chip and configured to have a width less than that of the power pads. The signal pads and the power pads are placed in the uppermost wiring layer among a plurality of wiring layers. Signal wiring connecting I/O cells and signal pads is disposed in the uppermost wiring layer. First power wiring electrically connecting the I/O cells and first power pads is disposed in the uppermost wiring layer. Second power wiring connecting internal circuits and second power pads is disposed in the uppermost wiring layer.

    摘要翻译： 一种改进的可线性，更少的布线层数和强化电源的半导体集成电路器件包括放置在半导体芯片上的多个电源焊盘和放置在半导体芯片上的多个信号焊盘，并且被配置为具有小于 电源垫。 信号焊盘和电源焊盘被放置在多个布线层中的最上层布线层中。 连接I / O单元和信号垫的信号线布置在最上层布线层中。 电连接I / O单元和第一功率垫的第一功率配线布置在最上层布线层中。 连接内部电路和第二电源焊盘的第二电源配线设置在最上层布线层中。