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1.发明授权公开(公告)号：US07551001B2
公开(公告)日：2009-06-23
申请号：US11667302
申请日：2006-10-02
IPC分类号： H03K19/173
CPC分类号： H03K19/1774 , G06F17/5054
摘要： A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.
摘要翻译： 多个逻辑元件组LEG11至LEG33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组（例如LEG11和LEG12）之间，终端中的时钟输出端子和时钟经由线路连接，而数据输出端子和端子中的数据通过延迟元件101连接。逻辑元件组 因此，LEG11至LEG33在时序设计方面彼此独立。 因此，如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计，则可以仅设计新的电路并将其连接到现有的电路，或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。
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2.发明申请公开(公告)号：US20080061834A1
公开(公告)日：2008-03-13
申请号：US11667302
申请日：2006-10-02
IPC分类号： H03K19/00
CPC分类号： H03K19/1774 , G06F17/5054
摘要： A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.
摘要翻译： 多个逻辑元件组LEG 11至LEG 33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组（例如LEG 11和LEG 12）之间，终端中的时钟输出端和时钟通过线连接，而终端中的数据输出端和数据通过延迟元件101连接。逻辑 元素组LEG 11至LEG 33在时序设计方面因此彼此独立。 因此，如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计，则可以仅设计新的电路并将其连接到现有的电路，或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。
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公开(公告)号：US06879193B2
公开(公告)日：2005-04-12
申请号：US10484904
申请日：2002-11-20
CPC分类号： G06F1/24
摘要： In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.
摘要翻译： 在作为断电对象的电路块110中，电压检测电路130和134分别设置在电源端子140和142附近，并且电压检测电路132和136设置在远离端子140的给定位置处， 142分别在两个电源系统的电源线141和143上。 电压检测电路仅由MOS晶体管构成。 在再次接通电源电路150的电源时，在所有电压检测电路检测到电源电压达到预定电位之后，复位信号产生电路160停止向电路块110输入复位信号 因此，由于在电源电压到达预定电压之后停止复位状态，因此半导体集成电路被正常初始化。 这提供了能够适当地产生上电复位信号的半导体集成电路。
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公开(公告)号：US20080042687A1
公开(公告)日：2008-02-21
申请号：US10581024
申请日：2005-03-10
申请人： Atsuhiro Mori , Shinichi Marui , Minoru Okamoto
发明人： Atsuhiro Mori , Shinichi Marui , Minoru Okamoto
IPC分类号： H03K19/177
CPC分类号： H01L27/118
摘要： The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced.In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.
摘要翻译： 可以减少由可编程逻辑元件形成的可编程逻辑器件的功耗和面积。 在由可编程逻辑元件形成的可编程逻辑器件101中，提供了第一逻辑元件102和第二逻辑元件104，其具有与第一逻辑元件102相同的逻辑，但具有被设计为低于 第一逻辑元件102。
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5.发明授权Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture 有权用于控制和提供相位时钟信号到具有多处理器架构的集成电路的组件的装置公开(公告)号：US06928575B2
公开(公告)日：2005-08-09
申请号：US09973888
申请日：2001-10-11
摘要： A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.
摘要翻译： 第一处理器，第二处理器，存储器和时钟提供单元在单个芯片上集成在一起。 第一个处理器与第一个内部时钟信号同步工作。 第二处理器与第二内部时钟信号同步工作。 存储器与第三个内部时钟信号同步工作。 时钟供应单元从外部时钟信号产生三个彼此同相的时钟信号，并将这些时钟信号作为第一，第二和第三内部时钟信号提供。 第一和第二处理器通过数据总线共享存储器。 每个处理器都有一个内部复位信号。
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公开(公告)号：US07492184B2
公开(公告)日：2009-02-17
申请号：US10581024
申请日：2005-03-10
申请人： Atsuhiro Mori , Shinichi Marui , Minoru Okamoto
发明人： Atsuhiro Mori , Shinichi Marui , Minoru Okamoto
IPC分类号： H03K19/173
CPC分类号： H01L27/118
摘要： The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced.In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.
摘要翻译： 可以减少由可编程逻辑元件形成的可编程逻辑器件的功耗和面积。 在由可编程逻辑元件形成的可编程逻辑器件101中，提供了第一逻辑元件102和第二逻辑元件104，其具有与第一逻辑元件102相同的逻辑，但具有被设计为低于 第一逻辑元件102。
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公开(公告)号：US08452985B2
公开(公告)日：2013-05-28
申请号：US11886712
申请日：2006-04-07
CPC分类号： H04L9/0891 , H04L2209/60
摘要： The present invention provides an apparatus for securely acquiring a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatus includes an FPGA that is reconfigurable. The content playback apparatus stores a decryption circuit program that shows the structure of a decryption circuit that executes decryption in accordance with a prescribed cryptosystem. The FPGA is reconfigured in accordance with the program to configure the decryption circuit. The playback apparatus acquires, from outside, an encrypted file that has been generated by encrypting a file including a decryption circuit program corresponding to the new cryptosystem in accordance with the prescribed cryptosystem, and decrypts the encrypted file by the decryption circuit.
摘要翻译： 本发明提供一种用于安全地获取与新密码系统对应的电路配置信息集的装置，而不增加可重构电路的数量。 内容播放装置包括可重新配置的FPGA。 内容重放装置存储解密电路程序，其显示根据规定的密码系统执行解密的解密电路的结构。 根据程序重新配置FPGA以配置解密电路。 回放装置从外部获取通过根据规定的密码系统加密包含与新密码系统相对应的解密电路程序的文件而生成的加密文件，并且通过解密电路解密加密文件。
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公开(公告)号：US20090055638A1
公开(公告)日：2009-02-26
申请号：US11918656
申请日：2006-04-21
IPC分类号： G06F15/177 , G06F17/30
CPC分类号： G06F21/602 , G06F21/10 , H04L9/08 , H04L9/32 , H04L2209/60
摘要： A design data storage unit stores a plurality of pieces of design data. A judgment unit 203 judges whether a circuit for decrypting an encrypted content received from a content server 10 is realized in a reconfigurable unit 208, and judges whether a piece of the design data for realizing the circuit for decrypting the encrypted content is held. If the desired circuit is not realized in the reconfigurable unit 208 and the desired piece of the design data is not held, the desired piece of the design data is acquired from a design data server 30 via a network.
摘要翻译： 设计数据存储单元存储多条设计数据。 判断单元203判断在可重新配置单元208中是否实现了用于解密从内容服务器10接收到的加密内容的电路，并且判断用于实现用于解密加密内容的电路的设计数据是否被保持。 如果在可重配置单元208中没有实现期望的电路，并且不保持期望的设计数据，则从设计数据服务器30经由网络获取期望的设计数据。
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公开(公告)号：US20090067632A1
公开(公告)日：2009-03-12
申请号：US11918628
申请日：2006-04-21
CPC分类号： H04L9/0894
摘要： An information processing apparatus is provided with a reconfigurable unit (101) in which a circuit can be reconfigured. The provision of a generation unit (103) enables the generation of design data of a circuit configured by the reconfigurable unit (101), and enables a reduction in the amount of design data to be held by a design data storage unit (102).
摘要翻译： 信息处理装置设置有可重新配置电路的可重构单元（101）。 提供生成单元（103）能够生成由可重构单元（101）配置的电路的设计数据，并且能够减少由设计数据存储单元（102）保持的设计数据量。
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公开(公告)号：US06643749B2
公开(公告)日：2003-11-04
申请号：US09985285
申请日：2001-11-02
申请人： Shinichi Marui
发明人： Shinichi Marui
IPC分类号： G06F1200
CPC分类号： G06F15/163
摘要： Each of processors has an input/output port provided with a data terminal for transmitting and receiving address information and data to be transferred, a mode terminal for transmitting and receiving a mode signal indicative of whether a signal at the data terminal represents the address information or the data to be transmitted, a read/write terminal for transmitting and receiving a read/write signal indicative of a timing for each of the signal at the data terminal and a signal at the mode terminal, an input buffer and an output buffer each connected to the data terminal, a data memory pointer connected to the internal data memory, and a control circuit connected to the mode terminal and to the read/write terminal.
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