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1.发明授权Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture 有权用于控制和提供相位时钟信号到具有多处理器架构的集成电路的组件的装置公开(公告)号：US06928575B2
公开(公告)日：2005-08-09
申请号：US09973888
申请日：2001-10-11
摘要： A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.
摘要翻译： 第一处理器，第二处理器，存储器和时钟提供单元在单个芯片上集成在一起。 第一个处理器与第一个内部时钟信号同步工作。 第二处理器与第二内部时钟信号同步工作。 存储器与第三个内部时钟信号同步工作。 时钟供应单元从外部时钟信号产生三个彼此同相的时钟信号，并将这些时钟信号作为第一，第二和第三内部时钟信号提供。 第一和第二处理器通过数据总线共享存储器。 每个处理器都有一个内部复位信号。
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公开(公告)号：US06879193B2
公开(公告)日：2005-04-12
申请号：US10484904
申请日：2002-11-20
CPC分类号： G06F1/24
摘要： In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.
摘要翻译： 在作为断电对象的电路块110中，电压检测电路130和134分别设置在电源端子140和142附近，并且电压检测电路132和136设置在远离端子140的给定位置处， 142分别在两个电源系统的电源线141和143上。 电压检测电路仅由MOS晶体管构成。 在再次接通电源电路150的电源时，在所有电压检测电路检测到电源电压达到预定电位之后，复位信号产生电路160停止向电路块110输入复位信号 因此，由于在电源电压到达预定电压之后停止复位状态，因此半导体集成电路被正常初始化。 这提供了能够适当地产生上电复位信号的半导体集成电路。
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公开(公告)号：US06751773B2
公开(公告)日：2004-06-15
申请号：US09833061
申请日：2001-04-12
IPC分类号： H03M1303
CPC分类号： H03M13/23
摘要： A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.
摘要翻译： 编码装置包括移位寄存器，输入寄存器和逻辑运算部。 移位寄存器在输入位序列上执行位移位，并将输入位序列的一位相继存储。 输入寄存器存储关于生成多项式的各个阶的项的系数。 逻辑运算部分获得存储在移位寄存器上的相应位的逻辑积和存储在输入寄存器上的相关位以及输入到移位寄存器的每一位的逻辑积和存储在输入寄存器上的关联位， 输入一位输入比特序列，输入比特关联的多项式项中的系数中的高阶一个。 接下来，逻辑运算部分导出乘积的异或逻辑和，然后输出和作为代码序列的位。
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4.发明申请公开(公告)号：US20080061834A1
公开(公告)日：2008-03-13
申请号：US11667302
申请日：2006-10-02
IPC分类号： H03K19/00
CPC分类号： H03K19/1774 , G06F17/5054
摘要： A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.
摘要翻译： 多个逻辑元件组LEG 11至LEG 33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组（例如LEG 11和LEG 12）之间，终端中的时钟输出端和时钟通过线连接，而终端中的数据输出端和数据通过延迟元件101连接。逻辑 元素组LEG 11至LEG 33在时序设计方面因此彼此独立。 因此，如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计，则可以仅设计新的电路并将其连接到现有的电路，或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。
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公开(公告)号：US20080042687A1
公开(公告)日：2008-02-21
申请号：US10581024
申请日：2005-03-10
申请人： Atsuhiro Mori , Shinichi Marui , Minoru Okamoto
发明人： Atsuhiro Mori , Shinichi Marui , Minoru Okamoto
IPC分类号： H03K19/177
CPC分类号： H01L27/118
摘要： The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced.In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.
摘要翻译： 可以减少由可编程逻辑元件形成的可编程逻辑器件的功耗和面积。 在由可编程逻辑元件形成的可编程逻辑器件101中，提供了第一逻辑元件102和第二逻辑元件104，其具有与第一逻辑元件102相同的逻辑，但具有被设计为低于 第一逻辑元件102。
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公开(公告)号：US07492184B2
公开(公告)日：2009-02-17
申请号：US10581024
申请日：2005-03-10
申请人： Atsuhiro Mori , Shinichi Marui , Minoru Okamoto
发明人： Atsuhiro Mori , Shinichi Marui , Minoru Okamoto
IPC分类号： H03K19/173
CPC分类号： H01L27/118
摘要： The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced.In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.
摘要翻译： 可以减少由可编程逻辑元件形成的可编程逻辑器件的功耗和面积。 在由可编程逻辑元件形成的可编程逻辑器件101中，提供了第一逻辑元件102和第二逻辑元件104，其具有与第一逻辑元件102相同的逻辑，但具有被设计为低于 第一逻辑元件102。
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公开(公告)号：US08723777B2
公开(公告)日：2014-05-13
申请号：US13560682
申请日：2012-07-27
CPC分类号： G09G3/2096 , G09G3/2003 , G09G3/3611 , G09G2340/02 , G09G2340/145
摘要： A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.
摘要翻译： 面板控制装置包括可编程阵列。 该可编程阵列根据配置代码进行操作并且包括多个第一类元素和至少一个第二类元素。 这提供了一种面板控制装置，其需要小的电路面积，适用于系统级芯片（SoC）安装，并且在将来也驱动具有各种规格的液晶显示装置。
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8.发明授权Method of configuring information processing system and semiconductor integrated circuit 失效配置信息处理系统和半导体集成电路的方法公开(公告)号：US07536289B2
公开(公告)日：2009-05-19
申请号：US11071465
申请日：2005-03-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.
摘要翻译： 一种根据本发明的信息处理系统的配置方法，在用于实现一个或多个应用的信息处理系统中，包括：对于每个确定的处理级别并输入模型的所有应用进行建模的步骤，步骤 输入表示输入模型的不变性的参数的步骤，使用应用模型和表示不变性的参数作为输入信息并将表示不变性的参数与边界条件进行比较的步骤，以及将应用模型之一分配给可编程 逻辑和另一个应用模型基于比较结果的专用硬件。
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公开(公告)号：US06754870B2
公开(公告)日：2004-06-22
申请号：US09833787
申请日：2001-04-13
IPC分类号： H03M1300
CPC分类号： H03M13/091 , G06F9/3879 , H03M13/6516 , H03M13/6569
摘要： To enable high-speed CRC operation and flexible use of various generating polynomials without causing significant increase in circuit scale, the CRC operation unit uses circuits generally provided for a DSP and some additional circuits. The CRC operation unit includes: a generating polynomial supply section having a first general register for storing an arbitrary generating polynomial and a selector for selectively outputting the generating polynomial or data of which all bits has a value of 0; an operation data supply section having a memory, a shift register, a second general register, and a barrel shifter, for outputting operation data for CRC operation based on transmitting/receiving data; an operation section for performing CRC operation using the generating polynomial output from the generating polynomial supply section and the operation data output from the operation data supply section; and an operation instruction execution control section for controlling the operations of the above sections.
摘要翻译： 为了实现高速CRC操作和灵活使用各种生成多项式而不引起电路规模的显着增加，CRC操作单元使用通常为DSP提供的电路和一些附加电路。 CRC操作单元包括：生成多项式提供部分，具有用于存储任意生成多项式的第一通用寄存器和用于选择性地输出所有位具有值0的生成多项式或数据的选择器; 具有存储器，移位寄存器，第二通用寄存器和桶形移位器的操作数据提供部分，用于基于发送/接收数据输出用于CRC操作的操作数据; 操作部分，用于使用从生成多项式提供部分输出的生成多项式和从操作数据提供部分输出的操作数据来执行CRC操作; 以及操作指令执行控制部分，用于控制上述部分的操作。
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10.发明授权公开(公告)号：US07551001B2
公开(公告)日：2009-06-23
申请号：US11667302
申请日：2006-10-02
IPC分类号： H03K19/173
CPC分类号： H03K19/1774 , G06F17/5054
摘要： A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.
摘要翻译： 多个逻辑元件组LEG11至LEG33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组（例如LEG11和LEG12）之间，终端中的时钟输出端子和时钟经由线路连接，而数据输出端子和端子中的数据通过延迟元件101连接。逻辑元件组 因此，LEG11至LEG33在时序设计方面彼此独立。 因此，如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计，则可以仅设计新的电路并将其连接到现有的电路，或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。
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