Reconfigurable semiconductor integrated circuit and processing assignment method for the same
    1.
    发明授权
    Reconfigurable semiconductor integrated circuit and processing assignment method for the same 有权
    可重构半导体集成电路和处理分配方法相同

    公开(公告)号:US07551001B2

    公开(公告)日:2009-06-23

    申请号:US11667302

    申请日:2006-10-02

    IPC分类号: H03K19/173

    CPC分类号: H03K19/1774 G06F17/5054

    摘要: A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

    摘要翻译: 多个逻辑元件组LEG11至LEG33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组(例如LEG11和LEG12)之间,终端中的时钟输出端子和时钟经由线路连接,而数据输出端子和端子中的数据通过延迟元件101连接。逻辑元件组 因此,LEG11至LEG33在时序设计方面彼此独立。 因此,如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计,则可以仅设计新的电路并将其连接到现有的电路,或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。

    RECONFIGURABLE SEMICONDUCTOR INTERGRATED CIRCUIT AND PROCESSING ASSIGNMENT METHOD FOR THE SAME
    2.
    发明申请
    RECONFIGURABLE SEMICONDUCTOR INTERGRATED CIRCUIT AND PROCESSING ASSIGNMENT METHOD FOR THE SAME 有权
    可重构半导体集成电路及其加工分配方法

    公开(公告)号:US20080061834A1

    公开(公告)日:2008-03-13

    申请号:US11667302

    申请日:2006-10-02

    IPC分类号: H03K19/00

    CPC分类号: H03K19/1774 G06F17/5054

    摘要: A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

    摘要翻译: 多个逻辑元件组LEG 11至LEG 33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组(例如LEG 11和LEG 12)之间,终端中的时钟输出端和时钟通过线连接,而终端中的数据输出端和数据通过延迟元件101连接。逻辑 元素组LEG 11至LEG 33在时序设计方面因此彼此独立。 因此,如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计,则可以仅设计新的电路并将其连接到现有的电路,或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。

    Programmable Logic Device and Method for Designing the Same
    3.
    发明申请
    Programmable Logic Device and Method for Designing the Same 有权
    可编程逻辑器件及其设计方法

    公开(公告)号:US20080042687A1

    公开(公告)日:2008-02-21

    申请号:US10581024

    申请日:2005-03-10

    IPC分类号: H03K19/177

    CPC分类号: H01L27/118

    摘要: The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced.In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.

    摘要翻译: 可以减少由可编程逻辑元件形成的可编程逻辑器件的功耗和面积。 在由可编程逻辑元件形成的可编程逻辑器件101中,提供了第一逻辑元件102和第二逻辑元件104,其具有与第一逻辑元件102相同的逻辑,但具有被设计为低于 第一逻辑元件102。

    Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture
    4.
    发明授权
    Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture 有权
    用于控制和提供相位时钟信号到具有多处理器架构的集成电路的组件的装置

    公开(公告)号:US06928575B2

    公开(公告)日:2005-08-09

    申请号:US09973888

    申请日:2001-10-11

    IPC分类号: G11C7/22 G06F1/12

    CPC分类号: G11C7/222 G11C7/22

    摘要: A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.

    摘要翻译: 第一处理器,第二处理器,存储器和时钟提供单元在单个芯片上集成在一起。 第一个处理器与第一个内部时钟信号同步工作。 第二处理器与第二内部时钟信号同步工作。 存储器与第三个内部时钟信号同步工作。 时钟供应单元从外部时钟信号产生三个彼此同相的时钟信号,并将这些时钟信号作为第一,第二和第三内部时钟信号提供。 第一和第二处理器通过数据总线共享存储器。 每个处理器都有一个内部复位信号。

    Programmable logic device and method for designing the same
    5.
    发明授权
    Programmable logic device and method for designing the same 有权
    可编程逻辑器件及其设计方法

    公开(公告)号:US07492184B2

    公开(公告)日:2009-02-17

    申请号:US10581024

    申请日:2005-03-10

    IPC分类号: H03K19/173

    CPC分类号: H01L27/118

    摘要: The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced.In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.

    摘要翻译: 可以减少由可编程逻辑元件形成的可编程逻辑器件的功耗和面积。 在由可编程逻辑元件形成的可编程逻辑器件101中,提供了第一逻辑元件102和第二逻辑元件104,其具有与第一逻辑元件102相同的逻辑,但具有被设计为低于 第一逻辑元件102。

    Semiconductor integrated circuit and its reset method
    6.
    发明授权
    Semiconductor integrated circuit and its reset method 有权
    半导体集成电路及其复位方法

    公开(公告)号:US06879193B2

    公开(公告)日:2005-04-12

    申请号:US10484904

    申请日:2002-11-20

    IPC分类号: G06F1/24 H03K17/22 H03L7/00

    CPC分类号: G06F1/24

    摘要: In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

    摘要翻译: 在作为断电对象的电路块110中,电压检测电路130和134分别设置在电源端子140和142附近,并且电压检测电路132和136设置在远离端子140的给定位置处, 142分别在两个电源系统的电源线141和143上。 电压检测电路仅由MOS晶体管构成。 在再次接通电源电路150的电源时,在所有电压检测电路检测到电源电压达到预定电位之后,复位信号产生电路160停止向电路块110输入复位信号 因此,由于在电源电压到达预定电压之后停止复位状态,因此半导体集成电路被正常初始化。 这提供了能够适当地产生上电复位信号的半导体集成电路。

    Coding apparatus capable of high speed operation
    8.
    发明授权
    Coding apparatus capable of high speed operation 有权
    能够高速运行的编码装置

    公开(公告)号:US06751773B2

    公开(公告)日:2004-06-15

    申请号:US09833061

    申请日:2001-04-12

    IPC分类号: H03M1303

    CPC分类号: H03M13/23

    摘要: A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.

    摘要翻译: 编码装置包括移位寄存器,输入寄存器和逻辑运算部。 移位寄存器在输入位序列上执行位移位,并将输入位序列的一位相继存储。 输入寄存器存储关于生成多项式的各个阶的项的系数。 逻辑运算部分获得存储在移位寄存器上的相应位的逻辑积和存储在输入寄存器上的相关位以及输入到移位寄存器的每一位的逻辑积和存储在输入寄存器上的关联位, 输入一位输入比特序列,输入比特关联的多项式项中的系数中的高阶一个。 接下来,逻辑运算部分导出乘积的异或逻辑和,然后输出和作为代码序列的位。

    Processing unit and processing method
    9.
    发明授权
    Processing unit and processing method 有权
    处理单元及处理方法

    公开(公告)号:US06477661B2

    公开(公告)日:2002-11-05

    申请号:US09974807

    申请日:2001-10-12

    IPC分类号: G06F1100

    摘要: A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.

    摘要翻译: 提供了一种操作数字信号处理器的方法。 数字信号处理器可以被提供为无线电通信移动台,无线电通信基站装置或CDMA无线电通信系统。 将旧状态的每个路径度量PM1和PM0分别添加到每个分支量度BM1和BM0。 通过将PM1 + BM1的值与PM0 + BM0的值进行比较来形成新状态N的路径度量。 通过将PM1 + BM0的值与PM0 + BM1进行比较来形成新状态N + 2k-2的路径度量。

    Accessing multiple memories using address conversion among multiple addresses

    公开(公告)号:US06289429B1

    公开(公告)日:2001-09-11

    申请号:US08812711

    申请日:1997-03-06

    申请人: Minoru Okamoto

    发明人: Minoru Okamoto

    IPC分类号: G06F1200

    摘要: A memory device including a first memory and a second memory. A first processor generates a first address for defining a location to be accessed in the first memory and a second address for defining a location to be accessed in the second memory. A second processor generates a third address. A memory control section controls access to the first memory and access to the second memory. The memory control section includes an address conversion section for converting the third address so as to represent either one of the first address and the second address.