公开(公告)号：US07799644B2

公开(公告)日：2010-09-21

申请号：US11460782

申请日：2006-07-28

申请人： Ted R. White ,  James D. Burnett ,  Brian A. Winstead

发明人： Ted R. White ,  James D. Burnett ,  Brian A. Winstead

IPC分类号： H01L21/8234 ,  H01L21/44

CPC分类号： H01L21/823835 ,  H01L21/823814 ,  H01L27/0922

摘要： A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region for controlling electrical conduction of the transistor. A drain region is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.

摘要翻译： 具有比漏极更高电阻的源极的晶体管作为存储电路中的上拉器件是最佳的。 晶体管具有源极区域，源极源极具有源极电阻。 来源地区没有水淹。 控制电极区域与源极区域相邻，用于控制晶体管的导电。 漏极区域与控制电极区域相邻并与源极区域相对。 漏极区域具有被浸没并具有漏极电阻的漏极注入。 源极电阻大于漏极电阻，因为源极区域具有不同于漏极区域的物理性质。

公开(公告)号：US20080026529A1

公开(公告)日：2008-01-31

申请号：US11460782

申请日：2006-07-28

申请人： Ted R. White ,  James D. Burnett ,  Brian A. Winstead

发明人： Ted R. White ,  James D. Burnett ,  Brian A. Winstead

IPC分类号： H01L21/8234

CPC分类号： H01L21/823835 ,  H01L21/823814 ,  H01L27/0922

摘要： A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region for controlling electrical conduction of the transistor. A drain region is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.

摘要翻译： 具有比漏极更高电阻的源极的晶体管作为存储电路中的上拉器件是最佳的。 晶体管具有源极区域，源极源极具有源极电阻。 来源地区没有水淹。 控制电极区域与源极区域相邻，用于控制晶体管的导电。 漏极区域与控制电极区域相邻并与源极区域相对。 漏极区域具有被浸没并具有漏极电阻的漏极注入。 源极电阻大于漏极电阻，因为源极区域具有不同于漏极区域的物理性质。

公开(公告)号：US07479422B2

公开(公告)日：2009-01-20

申请号：US11373536

申请日：2006-03-10

申请人： Brian A. Winstead ,  Ted R. White ,  Da Zhang

发明人： Brian A. Winstead ,  Ted R. White ,  Da Zhang

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.

摘要翻译： 一种形成半导体器件的方法包括提供具有第一材料和覆盖第一材料的第二材料的衬底区域，其中第一材料具有与第二材料的晶格常数不同的晶格常数。 该方法还包括蚀刻栅极的第一侧上的第一开口并蚀刻栅极的第二侧上的第二开口。 该方法还包括在第一开口和第二开口中产生第一原位p型掺杂外延区域，其中使用第二材料产生第一原位掺杂外延区域。 该方法还包括在第一开口和第二开口中形成覆盖第一原位p型掺杂外延区域的第二原位n型掺杂截留区域，其中第二原位n型掺杂外延区域是 使用第二种材料创建。

公开(公告)号：US20080111153A1

公开(公告)日：2008-05-15

申请号：US11559642

申请日：2006-11-14

申请人： Brian A. Winstead ,  Ted R. White

发明人： Brian A. Winstead ,  Ted R. White

IPC分类号： H01L29/78 ,  H01L21/04

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78687

摘要： An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with the associated channel region, and the heterojunction region can lie along a surface of a semiconductor layer closer to a substrate than an opposing surface of the substrate. The electronic device can also include an n-channel transistor, and the subthreshold carrier depth of the p-channel and n-channel transistors can have approximately a same value as compared to each other. A process of forming the electronic device can include forming a compound semiconductor layer having an energy band gap greater than approximately 1.2 eV.

摘要翻译： 电子器件可以包括具有第一沟道区的第一晶体管，第一沟道区还包括在一个方面为至多约5nm厚的异质结区。 在另一方面，第一晶体管可以包括p沟道晶体管，其包括具有与相关沟道区不匹配的功函数的栅电极，并且异质结区可以沿着比相对表面更靠近衬底的半导体层的表面 的基底。 电子设备还可以包括n沟道晶体管，并且p沟道和n沟道晶体管的亚阈值载流子深度可以具有与彼此相差大致相同的值。 形成电子器件的方法可以包括形成具有大于约1.2eV的能带隙的化合物半导体层。

公开(公告)号：US08163615B1

公开(公告)日：2012-04-24

申请号：US13052529

申请日：2011-03-21

申请人： Ted R. White ,  Gowrishankar L. Chindalore ,  Brian A. Winstead

发明人： Ted R. White ,  Gowrishankar L. Chindalore ,  Brian A. Winstead

IPC分类号： H01L21/336

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/7881

摘要： A method for forming a split-gate non-volatile memory (NVM) cell includes forming a first gate layer over a semiconductor substrate; forming a conductive layer over the first gate layer; patterning the first gate layer and the conductive layer to form a first sidewall, wherein the first sidewall comprises a sidewall of the first gate layer and a sidewall of the conductive layer; forming a first dielectric layer over the conductive layer and the semiconductor substrate, wherein the first dielectric layer overlaps the first sidewall; forming a second gate layer over the first dielectric layer, wherein the second gate layer is formed over the conductive layer and the first gate layer and overlaps the first sidewall; and patterning the first gate layer and the second gate layer to form a first gate and a second gate, respectively, of the split-gate NVM cell, wherein the second gate overlaps the first gate and a portion of the conductive layer remains between the first gate and the second gate.

摘要翻译： 一种分离栅极非易失性存储器（NVM）单元的形成方法包括在半导体衬底上形成第一栅极层; 在所述第一栅极层上形成导电层; 图案化第一栅极层和导电层以形成第一侧壁，其中第一侧壁包括第一栅极层的侧壁和导电层的侧壁; 在所述导电层和所述半导体衬底之上形成第一电介质层，其中所述第一电介质层与所述第一侧壁重叠; 在所述第一介电层上形成第二栅极层，其中所述第二栅极层形成在所述导电层和所述第一栅极层上并与所述第一侧壁重叠; 以及图案化所述第一栅极层和所述第二栅极层，以分别形成所述分裂栅极NVM单元的第一栅极和第二栅极，其中所述第二栅极与所述第一栅极重叠，并且所述导电层的一部分保留在所述第一栅极 门和第二门。

公开(公告)号：US09111908B2

公开(公告)日：2015-08-18

申请号：US13448531

申请日：2012-04-17

申请人： Ted R. White ,  Gowrishankar L. Chindalore ,  Brian A. Winstead

发明人： Ted R. White ,  Gowrishankar L. Chindalore ,  Brian A. Winstead

IPC分类号： H01L29/76 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/7881

摘要： Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

摘要翻译： 实施例包括形成为具有控制栅极和选择栅极的分离栅极非易失性存储器单元，其中控制栅极的至少一部分形成在选择栅极上。 在选择栅极和控制栅极之间形成电荷存储层。 选择栅极使用第一导电层和第二导电层形成。 第二导电层形成在第一导电层之上，并且具有比第一导电层更低的电阻率。 在一个实施例中，第一导电层是多晶硅，第二导电层是氮化钛（TiN）。 在另一个实施例中，第二导电层可以是硅化物或其它导电材料，或者具有比第一导电层低的电阻率的导电材料的组合。

公开(公告)号：US08390026B2

公开(公告)日：2013-03-05

申请号：US11559642

申请日：2006-11-14

申请人： Brian A. Winstead ,  Ted R. White

发明人： Brian A. Winstead ,  Ted R. White

IPC分类号： H01L29/78 ,  H01L21/04

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78687

摘要： An electronic device can include a first transistor having a first channel region further including a heterojunction region that, in one aspect, is at most approximately 5 nm thick. In another aspect, the first transistor can include a p-channel transistor including a gate electrode having a work function mismatched with the associated channel region, and the heterojunction region can lie along a surface of a semiconductor layer closer to a substrate than an opposing surface of the substrate. The electronic device can also include an n-channel transistor, and the subthreshold carrier depth of the p-channel and n-channel transistors can have approximately a same value as compared to each other. A process of forming the electronic device can include forming a compound semiconductor layer having an energy band gap greater than approximately 1.2 eV.

摘要翻译： 电子器件可以包括具有第一沟道区的第一晶体管，该第一沟道区还包括在一个方面为至多约5nm厚的异质结区。 在另一方面，第一晶体管可以包括p沟道晶体管，其包括具有与相关沟道区不匹配的功函数的栅极，并且异质结区可以沿着比相对表面更靠近衬底的半导体层的表面 的基底。 电子设备还可以包括n沟道晶体管，并且p沟道和n沟道晶体管的亚阈值载流子深度可以具有与彼此相差大致相同的值。 形成电子器件的方法可以包括形成具有大于约1.2eV的能带隙的化合物半导体层。

公开(公告)号：US07923769B2

公开(公告)日：2011-04-12

申请号：US12909027

申请日：2010-10-21

申请人： Ted R. White ,  Brian A. Winstead

发明人： Ted R. White ,  Brian A. Winstead

IPC分类号： H01L29/76

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/11521 ,  H01L29/42328

摘要： A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

公开(公告)号：US07923328B2

公开(公告)日：2011-04-12

申请号：US12103246

申请日：2008-04-15

申请人： Ted R. White ,  Brian A. Winstead

发明人： Ted R. White ,  Brian A. Winstead

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/11521 ,  H01L29/42328

摘要： A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

摘要翻译： 提供一种非易失性存储单元，其包括其中形成有源极区和限定在源极区和漏极区之间的沟道区的漏极区的衬底。 非易失性存储单元还包括覆盖通道区域的第一部分的选择栅极结构。 非易失性存储单元还包括形成在通道区域的第二部分上的控制栅极结构，其中控制栅极结构包括具有高度的纳米晶体堆叠，其中控制栅极结构在形成在 基本上平行于基板的顶表面的第一平面的交叉点和基本上平行于控制栅结构的侧表面的第二平面，其中，角区域中的控制栅结构的半径与 纳米晶体堆叠至少为0.5。

公开(公告)号：US20090256191A1

公开(公告)日：2009-10-15

申请号：US12103246

申请日：2008-04-15

申请人： Ted R. White ,  Brian A. Winstead

发明人： Ted R. White ,  Brian A. Winstead

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/11521 ,  H01L29/42328

摘要： A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

摘要翻译： 提供一种非易失性存储单元，其包括其中形成有源极区和限定在源极区和漏极区之间的沟道区的漏极区的衬底。 非易失性存储单元还包括覆盖通道区域的第一部分的选择栅极结构。 非易失性存储单元还包括形成在通道区域的第二部分上的控制栅极结构，其中控制栅极结构包括具有高度的纳米晶体堆叠，其中控制栅极结构在形成在 基本上平行于基板的顶表面的第一平面的交叉点和基本上平行于控制栅结构的侧表面的第二平面，其中，角区域中的控制栅结构的半径与 纳米晶体堆叠至少为0.5。