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1.发明授权公开(公告)号：US09111908B2
公开(公告)日：2015-08-18
申请号：US13448531
申请日：2012-04-17
IPC分类号： H01L29/76 , H01L29/423 , H01L21/28 , H01L27/115 , H01L29/788
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/7881
摘要： Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.
摘要翻译： 实施例包括形成为具有控制栅极和选择栅极的分离栅极非易失性存储器单元，其中控制栅极的至少一部分形成在选择栅极上。 在选择栅极和控制栅极之间形成电荷存储层。 选择栅极使用第一导电层和第二导电层形成。 第二导电层形成在第一导电层之上，并且具有比第一导电层更低的电阻率。 在一个实施例中，第一导电层是多晶硅，第二导电层是氮化钛（TiN）。 在另一个实施例中，第二导电层可以是硅化物或其它导电材料，或者具有比第一导电层低的电阻率的导电材料的组合。
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2.发明申请SEMICONDUCTOR DEVICE HAVING DIFFERENT NON-VOLATILE MEMORIES HAVING NANOCRYSTALS OF DIFFERING DENSITIES AND METHOD THEREFOR 有权具有不同浓度的纳米晶体的不同非挥发性记忆的半导体器件及其方法公开(公告)号：US20130193506A1
公开(公告)日：2013-08-01
申请号：US13362697
申请日：2012-01-31
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42332
摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
摘要翻译： 一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果 在第二密度中，其中第二密度大于第一密度。
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公开(公告)号：US08173505B2
公开(公告)日：2012-05-08
申请号：US12254331
申请日：2008-10-20
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11526 , H01L27/11536 , H01L27/11543 , H01L27/11573 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.
摘要翻译： 一种方法包括在半导体衬底上形成栅极材料的第一层; 在第一层上形成硬掩模层; 形成开口 在所述硬掩模层和所述开口内形成电荷存储层; 在所述电荷存储层上形成栅极材料的第二层; 去除所述第二层的一部分和所述电荷存储层的覆盖所述硬掩模层的部分，其中所述第二层的第二部分保留在所述开口内; 在所述硬掩模层上并在所述第二部分上形成图案化掩模层，其中所述图案化掩模层限定第一和第二位单元; 以及使用所述图案化掩模层形成所述第一和第二位单元，其中所述第一和第二位单元中的每一个包含由所述第一层制成的选择栅极和由所述第二层制成的控制栅极。
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4.发明授权Programming and erasing structure for a floating gate memory cell and method of making 有权浮动存储单元的编程和擦除结构及其制作方法公开(公告)号：US07745870B2
公开(公告)日：2010-06-29
申请号：US11626681
申请日：2007-01-24
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.
摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。 蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。 控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。 浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。 该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。 电子能够容易地在两层之间移动。 因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。
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5.发明授权Method of fabricating a storage device including decontinuous storage elements within and between trenches 有权制造包括槽内和沟槽之间的不连续存储元件的存储装置的方法公开(公告)号：US07592224B2
公开(公告)日：2009-09-22
申请号：US11393287
申请日：2006-03-30
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0458 , G11C2216/06 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.
摘要翻译： 半导体存储单元包括在半导体层中限定的第一沟槽下面的第一源极/漏极区域。 第二源极/漏极区域位于半导体层中的第二沟槽的下方。 第一沟槽中的第一选择栅极和第二沟槽中的第二选择栅极由选择栅极电介质排列。 电荷存储堆叠覆盖选择栅极，并且控制栅极覆盖堆叠。 DSE可以包括多晶硅的谨慎积累。 第一和第二选择栅极的上表面比第一和第二沟槽的上表面低。 控制栅极可以是垂直于选择栅极横穿并行进的连续控制栅极。 电池可以包括到半导体层的触点。 控制栅极可以包括覆盖第一选择栅极的第一控制栅极和覆盖第二选择栅极的第二控制栅极。
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公开(公告)号：US20090170262A1
公开(公告)日：2009-07-02
申请号：US12397905
申请日：2009-03-04
IPC分类号： H01L21/8239
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/926 , Y10S438/962
摘要： A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.
摘要翻译： 虚拟接地存储器阵列（VGA）由存储层上的存储层形成在衬底上，在存储层上方具有导电层。 根据图案化的光致抗蚀剂层打开导电层。 注入开口以在衬底中形成源极/漏极线，然后填充一层电介质材料。 然后进行化学机械抛光（CMP），直到暴露导电层的顶部。 这使得源极/漏极线之间的电介质间隔物和电介质间隔物之间的导电材料留下。 然后在导电材料和电介质间隔物上形成字线。 作为替代，代替使用导电层，使用在CMP步骤之后去除的牺牲层。 在去除牺牲部分之后，形成字线。 在这两种情况下，介质间隔物减少了栅极/漏极电容，并且从衬底到栅极的距离在通道上保持恒定。
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公开(公告)号：US20090111229A1
公开(公告)日：2009-04-30
申请号：US11931376
申请日：2007-10-31
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833
摘要： A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
摘要翻译： 一种方法通过提供半导体衬底并形成覆盖选择栅极形成分离栅极存储单元。 选择栅极具有预定的高度并且与半导体衬底电绝缘。 随后形成电荷存储层，覆盖并邻近选择栅极。 随后通过电荷存储层形成与选择栅极相邻并分离的控制栅极。 电荷存储层也位于控制栅极和半导体衬底之间。 控制门最初具有高于选择门的预定高度的高度。 控制栅极凹入到小于选择栅极的预定高度的控制栅极高度。 源极和漏极形成在半导体衬底中。
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公开(公告)号：US20090111226A1
公开(公告)日：2009-04-30
申请号：US11926348
申请日：2007-10-29
IPC分类号： H01L21/8239
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11526 , H01L27/11534 , H01L27/11536 , H01L27/11543 , H01L27/11573 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area.
摘要翻译： 提供了一种用于将非易失性存储器（NVM）电路与逻辑电路集成的方法。 该方法包括在NVM区域和衬底的逻辑区域上沉积第一层栅极材料层。 该方法还包括沉积包括彼此叠置的氮化物，氧化物和氮化物（ARC层）的多个邻接的牺牲层。 多个相邻的牺牲层用于在NVM区域中对存储晶体管的选择栅极和控制栅极进行图案化，并且多个相邻牺牲层的ARC层用于在逻辑区域中对逻辑晶体管的栅极进行图案化。
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9.发明授权公开(公告)号：US07285819B2
公开(公告)日：2007-10-23
申请号：US11188582
申请日：2005-07-25
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/4232 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7923
摘要： An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
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10.发明授权Process for operating an electronic device including a memory array and conductive lines 有权用于操作包括存储器阵列和导线的电子设备的工艺公开(公告)号：US07262997B2
公开(公告)日：2007-08-28
申请号：US11188898
申请日：2005-07-25
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译： 电子电路可以包括第一存储单元和第二存储单元。 在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。 源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。 在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。 在另一方面，第一和第二存储器单元连接到相同的位线。 当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。
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