公开(公告)号：US20130057245A1

公开(公告)日：2013-03-07

申请号：US13557793

申请日：2012-07-25

申请人： Teppei HIROTSU ,  Nobuyasu Kanekawa ,  Ryosuke Ishida ,  Tsutomu Yamada ,  Chihiro Sato

发明人： Teppei HIROTSU ,  Nobuyasu Kanekawa ,  Ryosuke Ishida ,  Tsutomu Yamada ,  Chihiro Sato

IPC分类号： G05F3/02

CPC分类号： H02M7/53803 ,  H02M3/1588 ,  H02M7/5395 ,  H02M2001/0009 ,  Y02B70/1466

摘要： A current regulator has a current regulating semiconductor device and a microcontroller which outputs a PWM pulse for driving a load to the current regulating semiconductor device and receives outputs of a high-side current detection circuit and a low-side current detection circuit from the current regulating semiconductor device. An output mixer of the current regulating semiconductor device switches, in synchronization with the PWM pulse, between the output of the high-side current detection circuit and the output of the low-side current detection circuit on one signal line to output the output to the microcontroller.

摘要翻译： 电流调节器具有电流调节半导体器件和微控制器，其输出用于将负载驱动到电流调节半导体器件的PWM脉冲，并且从电流调节器接收高侧电流检测电路和低侧电流检测电路的输出 半导体器件。 电流调节半导体装置的输出混频器与PWM脉冲同步地在高边电流检测电路的输出和低端电流检测电路的输出之间切换，以将输出输出到 微控制器

公开(公告)号：US20110049988A1

公开(公告)日：2011-03-03

申请号：US12855428

申请日：2010-08-12

申请人： Nobuyasu KANEKAWA ,  Teppei HIROTSU ,  Itaru TANABE ,  Shuichi MIYAOKA ,  Ryoichi OURA

发明人： Nobuyasu KANEKAWA ,  Teppei HIROTSU ,  Itaru TANABE ,  Shuichi MIYAOKA ,  Ryoichi OURA

IPC分类号： H02J4/00

CPC分类号： G05F1/46 ,  B60L2240/441 ,  B60L2240/445 ,  B60L2240/486 ,  B60W2510/0638 ,  B60W2510/0676 ,  B60W2540/10 ,  B60W2540/16 ,  Y10T307/445

摘要： The present invention aims to provide a control system which is capable of building high-precision current detecting means in a single-chip LSI and can be realized at a lower cost, and a semiconductor device used in the control system. Drive circuits are provided inside the same semiconductor chip. The drive circuits are equipped with: current detecting shunt resistors each of which is provided in each of the drive circuits and detects a current flowing through a load, the current detecting shunt resistors being provided within a semiconductor chip by the same process; a dummy resistor provided within the semiconductor chip by the same process as the current detecting shunt resistors; and a calibration reference externally attached to the semiconductor chip and connected to the dummy resistor. A correcting means corrects the values of currents that flow through the current detecting shunt resistors, using the dummy resistor and the calibration reference.

摘要翻译： 本发明旨在提供一种能够在单芯片LSI中构建高精度电流检测装置并且可以以较低成本实现的控制系统以及在控制系统中使用的半导体装置。 驱动电路设置在同一半导体芯片的内部。 驱动电路配备有电流检测分流电阻器，每个驱动电路设置在每个驱动电路中并检测流过负载的电流，电流检测分流电阻器通过相同的工艺设置在半导体芯片内; 通过与电流检测分流电阻器相同的工艺在半导体芯片内提供虚拟电阻器; 以及外部附接到半导体芯片并连接到虚拟电阻器的校准参考。 校正装置使用虚拟电阻器和校准基准校正流过电流检测分流电阻器的电流值。

公开(公告)号：US20070180317A1

公开(公告)日：2007-08-02

申请号：US11623441

申请日：2007-01-16

申请人： Teppei HIROTSU ,  Hiromichi Yamada ,  Teruaki Sakata ,  Kesami Hagiwara

发明人： Teppei HIROTSU ,  Hiromichi Yamada ,  Teruaki Sakata ,  Kesami Hagiwara

IPC分类号： G06F11/00

CPC分类号： G06F11/1407

摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.

摘要翻译： 该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，通过延迟的寄存器文件来恢复寄存器文件的内容，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态 该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。 该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。 结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令 。

公开(公告)号：US20120173850A1

公开(公告)日：2012-07-05

申请号：US13423145

申请日：2012-03-16

申请人： Teppei HIROTSU ,  Yuuichi ABE ,  Takeshi KATAOKA ,  Yasuhiro NAKATSUKA

发明人： Teppei HIROTSU ,  Yuuichi ABE ,  Takeshi KATAOKA ,  Yasuhiro NAKATSUKA

IPC分类号： G06F9/38 ,  G06F13/40 ,  G06F9/312

CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/382

摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

摘要翻译： 能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。 它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支 从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。 信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。