-
公开(公告)号：US06327198B1
公开(公告)日：2001-12-04
申请号：US09500087
申请日：2000-02-08
IPC分类号： G11C2900
CPC分类号： G11C29/12
摘要： A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.
摘要翻译： 根据本发明的半导体存储器件包括：测试模式设置电路，能够根据外部信号串行设置多个测试模式; 电压发生电路; 列相关控制电路; 一行相关控制电路; 和存储单元阵列。 在对应的测试模式中，奇数字线/偶数字线被带入选择/非选择状态。 在相应的测试模式中，在正常操作模式下，位线的电压被设定为高于均衡电压（内部电源电压）或更低（接地电压）。 因此，可以有效地写入检查图案。
-
公开(公告)号：US06288956B1
公开(公告)日：2001-09-11
申请号：US09477717
申请日：2000-01-05
IPC分类号： G11C1140
CPC分类号： G11C29/46
摘要： A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.
摘要翻译： 根据本发明的半导体器件包括多个测试模式电路。 每个测试模式电路包括解码输入信号和多个锁存电路的多个解码电路。 每个解码电路产生测试模式信号。 测试模式信号保持在锁存电路中。 每个测试模式电路还包括输出用于复位相应的锁存电路的组复位信号的解码电路。 因此，多个测试模式信号可以任意和连续地组合。
-
公开(公告)号：US06762967B2
公开(公告)日：2004-07-13
申请号：US10443775
申请日：2003-05-23
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译： 半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。 当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。 当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。 因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。
-
公开(公告)号：US06295238B1
公开(公告)日：2001-09-25
申请号：US09604007
申请日：2000-06-26
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译： 半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。 当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。 当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。 因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。
-
公开(公告)号：US06614713B2
公开(公告)日：2003-09-02
申请号：US09922670
申请日：2001-08-07
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C800
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译： 半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。 当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。 当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。 因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。
-
6.发明授权Semiconductor device including test-facilitating circuit using built-in self test circuit 有权半导体器件包括使用内置自检电路的测试便利电路公开(公告)号：US07032141B2
公开(公告)日：2006-04-18
申请号：US10198106
申请日：2002-07-19
申请人： Tetsushi Tanizaki
发明人： Tetsushi Tanizaki
IPC分类号： G11C29/00
摘要： A test interface circuit, which has a simple pattern generator mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three bits received from a tester, outputs an analysis result to a memory core and controls an operation of the memory core, and an address counter which counts addresses and outputs the addresses to the memory core in accordance with a counter control instruction of two bits received from the tester. It is, therefore, possible to make a circuit for testing the memory core small in scale and to decrease the number of pins for testing the memory core, so that it is possible to use an inexpensive tester and to reduce cost required to test the memory core.
摘要翻译： 具有安装在具有安装存储器的半导体器件上的简单图形发生器的测试接口电路由分析从测试器接收的三位指令的命令分析部分组成，将分析结果输出到存储器核心并控制 存储器核心的操作，以及根据从测试器接收的两个位的计数器控制指令对地址进行计数并将地址输出到存储器核心的地址计数器。 因此，可以制造用于小规模测试存储器芯片的电路并且减少用于测试存储器核心的引脚数量，使得可以使用廉价的测试器并且降低测试存储器所需的成本 核心。
-
7.发明授权Circuit for reducing test time and semiconductor memory device including the circuit 有权降低测试时间的电路和包括电路的半导体存储器件公开(公告)号：US06779139B2
公开(公告)日：2004-08-17
申请号：US09845494
申请日：2001-05-01
IPC分类号： G11C2900
CPC分类号： G11C29/44 , G01R31/318566 , G11C29/38
摘要： A semiconductor memory device includes: a determination section; an expected value control section; and an accumulation section. The determination section determines coincidence/non-coincidence between input data and an expected value. The expected value control section catches a read expected value in a read operation only. The accumulation section catches a determination result according to an accumulation-transmission signal. When the accumulation-transmission signal is in a transmission state, a determination result is caught, while when the accumulation-transmission signal enters an accumulation state, the next determination result is caught in a case of coincidence determination and once a non-coincidence determination result is caught, thereafter the non-coincidence determination result continues to be held.
摘要翻译： 半导体存储器件包括：确定部分; 预期价值控制部分; 和积累部分。 确定部分确定输入数据与期望值之间的一致/不一致。 期望值控制部分仅在读取操作中捕获读取期望值。 累积部根据累积发送信号来取得判定结果。 当累积发送信号处于发送状态时，判断结果被捕获，而当累计发送信号进入累加状态时，在一致判断的情况下，下一个确定结果被捕获，并且一旦不一致确定结果 被捕获，此后不合格确定结果继续保持。
-
8.发明授权Semiconductor test circuit for testing a semiconductor memory device having a write mask function 失效半导体测试电路，用于测试具有写掩码功能的半导体存储器件公开(公告)号：US06704229B2
公开(公告)日：2004-03-09
申请号：US10122365
申请日：2002-04-16
IPC分类号： G11C700
CPC分类号： G11C29/38 , G11C7/1006 , G11C29/36
摘要： In a test circuit for testing an eDRAM provided with a write mask function, eight internal expected values are generated based on a prescribed read data signal among read data signals of one unit of write mask (i.e., eight). Determination is performed as to whether the eight read data signals and the eight internal expected values respectively match or not, and when they match, the eight memory cells are determined to be normal. Thus, a multi-bit test can be performed even when a test pattern is written using a write mask function.
摘要翻译： 在用于测试具有写掩码功能的eDRAM的测试电路中，基于一个写入掩码（即八个）单位的读取数据信号中的规定的读取数据信号产生八个内部预期值。 执行关于八个读取数据信号和八个内部期望值是否分别匹配的确定，并且当它们匹配时，确定八个存储器单元是正常的。 因此，即使当使用写入掩码功能写入测试图案时，也可以执行多位测试。
-
9.发明授权Semiconductor memory device capable of increasing chip yields while maintaining rapid operation 失效半导体存储器件能够在保持快速操作的同时提高芯片产量
公开(公告)号：US5914907A
公开(公告)日：1999-06-22
申请号：US122760
申请日：1998-07-27
申请人： Mako Kobayashi , Tetsushi Tanizaki , Kazutami Arimoto , Teruhiko Amano , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Mitsuya Kinoshita
发明人： Mako Kobayashi , Tetsushi Tanizaki , Kazutami Arimoto , Teruhiko Amano , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Mitsuya Kinoshita
摘要： Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.
摘要翻译： 常规存储单元阵列被布置在除了位于第二行和第二列的区域之外的三行和三列的分割区域中。 位于第二行和第二列的交叉点的区域设置有冗余存储单元阵列。 为每个存储单元块提供具有冗余存储单元阵列的常规存储单元阵列的替换操作。
-
公开(公告)号：US20070180006A1
公开(公告)日：2007-08-02
申请号：US11698188
申请日：2007-01-26
IPC分类号： G06F15/00
CPC分类号： G06F13/1652 , G11C7/1006 , Y02D10/14
摘要： In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.
摘要翻译： 在并行运算处理装置中，具有布置在各自具有排列成行和列的多个存储单元的存储块之间的运算处理单元，各存储块的各列交替地与存储器的相对侧的运算处理单元连接 块。 通过在一个存储器块中选择一个字线，可以将数据传输到两个操作处理单元。 每个操作处理单元选择的字线数减少，功耗降低。 操作处理单元的位操作单元和读出放大器/写驱动器具有减轻的布置节距条件，并且数量减少，并且不需要存储器块之间的隔离区域，并且布局面积减小。 因此，具有布局面积和功耗降低的并行运算处理装置可以实现快速运行。
-
-
-
-
-
-
-
-
-
搜索结果
28 条记录 (耗时 0.031 秒)
