公开(公告)号：US5914907A

公开(公告)日：1999-06-22

申请号：US122760

申请日：1998-07-27

申请人： Mako Kobayashi ,  Tetsushi Tanizaki ,  Kazutami Arimoto ,  Teruhiko Amano ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Fukashi Morishita ,  Mitsuya Kinoshita

发明人： Mako Kobayashi ,  Tetsushi Tanizaki ,  Kazutami Arimoto ,  Teruhiko Amano ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Fukashi Morishita ,  Mitsuya Kinoshita

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C29/42 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C29/84

摘要： Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.

摘要翻译： 常规存储单元阵列被布置在除了位于第二行和第二列的区域之外的三行和三列的分割区域中。 位于第二行和第二列的交叉点的区域设置有冗余存储单元阵列。 为每个存储单元块提供具有冗余存储单元阵列的常规存储单元阵列的替换操作。

公开(公告)号：US06272034B1

公开(公告)日：2001-08-07

申请号：US09606402

申请日：2000-06-29

申请人： Mitsuya Kinoshita ,  Fukashi Morishita ,  Kazutami Arimoto ,  Takeshi Fujino ,  Tetsushi Tanizaki ,  Takahiro Tsuruda ,  Teruhiko Amano ,  Mako Kobayashi

发明人： Mitsuya Kinoshita ,  Fukashi Morishita ,  Kazutami Arimoto ,  Takeshi Fujino ,  Tetsushi Tanizaki ,  Takahiro Tsuruda ,  Teruhiko Amano ,  Mako Kobayashi

IPC分类号： G11C502

CPC分类号： G11C5/025

摘要： A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

摘要翻译： 控制存储器单元的操作的控制电路部分集中在中心部分，并且热辐射板通过粘合剂放置在其上。 具有MPU等的功能的半导体集成电路经由凸块电极放置在控制电路部分上方。 控制电路部分和存储块分别形成在分开的芯片上。

公开(公告)号：US06337506B2

公开(公告)日：2002-01-08

申请号：US09116887

申请日：1998-07-16

申请人： Fukashi Morishita ,  Teruhiko Amano ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Mitsuya Kinoshita ,  Mako Kobayashi

发明人： Fukashi Morishita ,  Teruhiko Amano ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Mitsuya Kinoshita ,  Mako Kobayashi

IPC分类号： H01L2900

CPC分类号： H01L23/552 ,  G11C5/14 ,  H01L21/761 ,  H01L23/585 ,  H01L27/0203 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.

摘要翻译： 噪声产生源的电源电路和振荡电路等被集中，其周边被保护环包围。 提供保护环以至少部分地具有接合焊盘。 利用焊盘下方的区域有效地提供保护环，从而在防止芯片面积的增加的同时实现有效的降噪。

公开(公告)号：US06215720B1

公开(公告)日：2001-04-10

申请号：US09478528

申请日：2000-01-06

申请人： Teruhiko Amano ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Mitsuya Kinoshita ,  Fukashi Morishita ,  Mako Kobayashi

发明人： Teruhiko Amano ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Mitsuya Kinoshita ,  Fukashi Morishita ,  Mako Kobayashi

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C5/025 ,  G11C7/22 ,  G11C8/12

摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

摘要翻译： 主控制电路通过四个本地控制电路提供对对应存储器块的访问。 存储块被布置成围绕主控制电路和本地控制电路。 控制信号到每个存储器块的延迟量被设置为基本上等于抑制控制信号中的偏斜。 可以实现高速DRAM。

公开(公告)号：US6072743A

公开(公告)日：2000-06-06

申请号：US110688

申请日：1998-07-07

申请人： Teruhiko Amano ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Mitsuya Kinoshita ,  Fukashi Morishita ,  Mako Kobayashi

发明人： Teruhiko Amano ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tetsushi Tanizaki ,  Takeshi Fujino ,  Mitsuya Kinoshita ,  Fukashi Morishita ,  Mako Kobayashi

IPC分类号： G11C5/02 ,  G11C7/22 ,  G11C8/12 ,  G11C8/00

CPC分类号： G11C7/222 ,  G11C5/025 ,  G11C7/22 ,  G11C8/12

摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

摘要翻译： 主控制电路通过四个本地控制电路提供对对应存储器块的访问。 存储块被布置成围绕主控制电路和本地控制电路。 将控制信号到每个存储块的延迟量设置为基本上等于抑制控制信号中的偏移。 可以实现高速DRAM。

公开(公告)号：US6064621A

公开(公告)日：2000-05-16

申请号：US113147

申请日：1998-07-10

申请人： Tetsushi Tanizaki ,  Mitsuya Kinoshita ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Fukashi Morishita ,  Teruhiko Amano ,  Kazutami Arimoto ,  Mako Kobayashi

发明人： Tetsushi Tanizaki ,  Mitsuya Kinoshita ,  Takeshi Fujino ,  Takahiro Tsuruda ,  Fukashi Morishita ,  Teruhiko Amano ,  Kazutami Arimoto ,  Mako Kobayashi

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C5/14 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C5/025 ,  G11C5/14 ,  G11C8/12

摘要： A rectangular semiconductor substrate region is divided into regions arranged in a plurality of rows and columns, and memory array blocks are provided to surround a central region. The plurality of memory array blocks are divided into a plurality of banks. Peripheral regions on both sides of the rectangular semiconductor substrate region are used as regions for providing sense amplifier power supply circuits, and circuits for generating a voltage to be transmitted onto word lines are provided at the four corner regions of the central region. Thus, a large storage capacity semiconductor memory device operating stably at a high speed and with reduced power consumption can be implemented.

摘要翻译： 矩形半导体衬底区域被分成多个行和列布置的区域，并且存储器阵列块被设置为围绕中心区域。 多个存储器阵列块被分成多个存储体。 矩形半导体衬底区域的两侧的周边区域被用作提供感测放大器电源电路的区域，并且在中心区域的四个角区域处设置用于产生要传输到字线上的电压的电路。 因此，可以实现以高速和低功耗稳定运行的大容量半导体存储器件。

公开(公告)号：US08638583B2

公开(公告)日：2014-01-28

申请号：US13621078

申请日：2012-09-15

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US08310852B2

公开(公告)日：2012-11-13

申请号：US13419217

申请日：2012-03-13

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

公开(公告)号：US20130010513A1

公开(公告)日：2013-01-10

申请号：US13621078

申请日：2012-09-15

申请人： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

公开(公告)号：US08164934B2

公开(公告)日：2012-04-24

申请号：US12720561

申请日：2010-03-09

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以增加搜索操作速度。