-
公开(公告)号：US06288956B1
公开(公告)日：2001-09-11
申请号：US09477717
申请日：2000-01-05
IPC分类号： G11C1140
CPC分类号： G11C29/46
摘要： A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.
摘要翻译： 根据本发明的半导体器件包括多个测试模式电路。 每个测试模式电路包括解码输入信号和多个锁存电路的多个解码电路。 每个解码电路产生测试模式信号。 测试模式信号保持在锁存电路中。 每个测试模式电路还包括输出用于复位相应的锁存电路的组复位信号的解码电路。 因此，多个测试模式信号可以任意和连续地组合。
-
公开(公告)号：US06327198B1
公开(公告)日：2001-12-04
申请号：US09500087
申请日：2000-02-08
IPC分类号： G11C2900
CPC分类号： G11C29/12
摘要： A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.
摘要翻译： 根据本发明的半导体存储器件包括：测试模式设置电路，能够根据外部信号串行设置多个测试模式; 电压发生电路; 列相关控制电路; 一行相关控制电路; 和存储单元阵列。 在对应的测试模式中，奇数字线/偶数字线被带入选择/非选择状态。 在相应的测试模式中，在正常操作模式下，位线的电压被设定为高于均衡电压（内部电源电压）或更低（接地电压）。 因此，可以有效地写入检查图案。
-
公开(公告)号：US5867446A
公开(公告)日：1999-02-02
申请号：US332626
申请日：1994-10-31
CPC分类号： G11C7/1072 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.
-
公开(公告)号：US5594704A
公开(公告)日：1997-01-14
申请号：US419566
申请日：1995-04-10
CPC分类号： G11C8/12 , G11C7/10 , G11C7/1006 , G11C7/1072
摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.
摘要翻译： 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止写入期望的位，如果数据写入应该是数据写入时，可以将数据集中写入所选择的存储器单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。
-
公开(公告)号：US5384745A
公开(公告)日：1995-01-24
申请号：US46333
申请日：1993-04-14
CPC分类号： G11C7/1072 , G11C7/10 , G11C7/1006 , G11C8/12
摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.
摘要翻译： 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止对所需位的写入，如果数据写入应当是数据写入时，可以将数据集中写入所选存储单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。
-
公开(公告)号：US08165499B2
公开(公告)日：2012-04-24
申请号：US12754732
申请日：2010-04-06
IPC分类号： G03G15/08
CPC分类号： G03G21/1647 , G03G15/1615 , G03G21/186 , G03G2221/1642 , G03G2221/1657
摘要： A unit detachably mountable to an apparatus main assembly is provided with a coupling for receiving a rotational driving force from the apparatus main assembly. Also the apparatus main assembly is provided with a coupling to be engaged with the coupling of the unit. At least one of these couplings can be pushed in a direction parallel to a rotation shaft and one of the couplings is provided with an inclined surface. During mounting and demounting of the unit, the engagement between the couplings is released by the pushing in of one of the couplings pushed by the inclined surface.
摘要翻译： 可拆卸地安装到设备主组件的单元设置有用于从设备主组件接收旋转驱动力的联接器。 而且，设备主组件还具有与单元的联接件接合的联接器。 这些联接器中的至少一个可以沿平行于旋转轴的方向推动，并且联接器中的一个设置有倾斜表面。 在安装和拆卸单元期间，通过推入由倾斜表面推动的联接器之一来释放联接器之间的接合。
-
公开(公告)号：US06727581B2
公开(公告)日：2004-04-27
申请号：US10242691
申请日：2002-09-13
申请人： Ryo Abe , Takayuki Miyamoto
发明人： Ryo Abe , Takayuki Miyamoto
IPC分类号： H01L2334
CPC分类号： H01L23/5382 , H01L25/0652 , H01L2224/48091 , H05K1/181 , H05K3/225 , H05K2201/10689 , H05K2203/1572 , Y02P70/611 , H01L2924/00014
摘要： In a case that a bare chip has been detected as being defective from among bare chips, a good chip is mounted to the rear surface of the surface wherein the bare chips are provided to a semiconductor module substrate so that a QFC pin of the bare chip is fixed at the ground potential (GND). Thereby, the bare chip stops the output of a signal to the input/output terminals or the input of a signal from the input/output terminals. As a result, the good chip outputs an electrical signal to the input/output terminals or an electrical signal is inputted from the input/output terminals. Thereby, a semiconductor module is gained that can be repaired even in the case that a defective chip is detected after the chip has been molded into a mold resin.
摘要翻译： 在裸芯片被检测为缺陷的情况下，将芯片安装到表面的后表面，其中将裸芯片设置到半导体模块基板，使得裸芯片的QFC引脚 固定在地电位（GND）。 因此，裸芯片停止对输入/输出端子的信号的输出或来自输入/输出端子的信号的输入。 结果，良好的芯片向输入/输出端子输出电信号，或者从输入/输出端子输入电信号。 从而，即使在芯片已经被模制成型树脂之后，在检测到有缺陷的芯片的情况下，也可以获得能够修复的半导体模块。
-
公开(公告)号：US06477348B2
公开(公告)日：2002-11-05
申请号：US09527692
申请日：2000-03-17
IPC分类号： G03G1501
CPC分类号： G03G15/0194 , G03G15/0189 , G03G2215/0119
摘要： An image forming apparatus including a plurality of image bearing members for bearing respective color images, and a transfer material bearing member for bearing and conveying a transfer material, wherein, at transfer positions where the image bearing members are contacted with the transfer material bearing member, the images on the image bearing members are successively transferred electrostatically onto the transfer material born on the transfer material bearing member in a superimposed fashion, and wherein a transfer material conveying path defined by the transfer material bearing member including the transfer positions is protruded toward a side opposite to a side on which the image bearing members are provided.
摘要翻译： 一种图像形成装置，包括用于承载各种彩色图像的多个图像承载部件和用于承载和输送转印材料的转印材料承载部件，其中，在图像承载部件与转印材料承载部件接触的转印位置处， 图像承载部件上的图像以叠加的方式连续转印到转印材料承载部件上的转印材料上，并且由包括转印位置的转印材料承载部件限定的转印材料输送路径朝向侧面突出 与设置有图像承载部件的一侧相对。
-
公开(公告)号：US6121806A
公开(公告)日：2000-09-19
申请号：US166909
申请日：1998-10-06
CPC分类号： G11C29/021 , G11C29/02 , G11C29/028 , G11C29/50 , G11C5/143 , G11C5/147 , G11C11/401 , G11C2029/5004
摘要： A level adjusting circuit for controlling a voltage supplied to a load such as a semiconductor device, which comprises a voltage level detecting circuit, a reference potential generating circuit for generating a pair of reference potential values to be output into the voltage level detecting circuit, and a monitor pad for drawing out the voltage supplied to the load, wherein the reference potential values are respectively used to compare with the voltage to thereby output a signal for starting supply of the voltage and a signal for ceasing the supply of the voltage under a usually used condition; and the voltage level detecting circuit is to compare either one of the reference potential values with the voltage or the other reference potential value with the voltage at a time under a testing condition, whereby the reference potential generating circuit can accurately be adjusted to change the reference potential values to render the voltage in a range permissible for operation of the load.
摘要翻译： 一种电平调节电路，用于控制提供给诸如半导体器件的负载的电压，其包括电压电平检测电路，用于产生要输出到电压电平检测电路的一对参考电位值的参考电位产生电路，以及 用于绘制提供给负载的电压的监视器焊盘，其中分别使用参考电位值与电压进行比较，从而输出用于开始电压供应的信号和用于停止在通常情况下提供电压的信号 使用条件; 并且电压电平检测电路将参考电位值与电压或其他参考电位值中的任一个与测试条件下的一次电压进行比较，从而可以精确地调整参考电位产生电路以改变参考值 将电压值置于负载运行允许范围内的电位值。
-
10.发明授权Semiconductor memory device capable of correctly and serially reading stored data signals 失效半导体存储器件能够正确和串行地读取存储的数据信号
公开(公告)号：US5367486A
公开(公告)日：1994-11-22
申请号：US765764
申请日：1991-09-26
申请人： Junji Mori , Takayuki Miyamoto
发明人： Junji Mori , Takayuki Miyamoto
IPC分类号： G11C8/04 , G11C7/10 , G11C11/401 , G11C11/4096 , G11C11/418 , H01L21/8242 , H01L27/108 , G11C13/00
CPC分类号： G11C11/4096 , G11C7/1051
摘要： In a serial memory, data signal holding circuits for temporarily holding data read from memory cells are provided as a data register. One holding circuit includes a latch circuit and capacitors connected to input/output nodes of the latch circuit, respectively. The capacitors contribute to stabilizing the latch function by the latch circuit. Therefore, when transistors turn on in response to a serial selection signal at a high level, the latch circuit is prevented from being inverted by the potentials of a serial bus line pair. Accordingly, generation of reading errors is prevented.
摘要翻译： 在串行存储器中，提供用于临时保存从存储单元读取的数据的数据信号保持电路作为数据寄存器。 一个保持电路包括分别与锁存电路的输入/输出节点连接的锁存电路和电容器。 电容器有助于通过锁存电路稳定锁存功能。 因此，当晶体管响应于高电平的串行选择信号而导通时，防止锁存电路被串行总线对的电位反相。 因此，防止读取错误的产生。
-
-
-
-
-
-
-
-
-
搜索结果
45 条记录 (耗时 0.039 秒)
