公开(公告)号：US06557150B1

公开(公告)日：2003-04-29

申请号：US09485169

申请日：2000-02-07

申请人： Tetsuroo Honmura ,  Takashi Nakajima ,  Kenzo Goto ,  Shoichi Watanabe

发明人： Tetsuroo Honmura ,  Takashi Nakajima ,  Kenzo Goto ,  Shoichi Watanabe

IPC分类号： G06K1750

CPC分类号： G06F17/5022

摘要： A method of extracting timing characteristics from transistor circuit data of modularity design products (a module) such as a CPU core in which the extracted timing characteristics are used for the timing verification of a circuit including a module to be extracted and timing constraints when logical synthesis or timing-driven layout is made. Particularly, since conditions fit for a timing rule of the module are included in timing characteristics when timing verification is executed by simulation, verification free of pseudo error is enabled. Also, the configuration of a timing characteristic library, a storage medium storing it and an LSI designing method using the storage medium are provided.

摘要翻译： 提供诸如CPU核心的模块化设计产品（模块）的晶体管电路数据的定时特性的方法，其中提取的定时特性被用于包括要提取的模块的电路的定时验证和当逻辑合成时的定时约束 或定时驱动布局。 特别地，由于当通过模拟执行定时验证时，由于适合于模块的定时规则的条件被包括在定时特性中，因此能够进行没有伪错误的验证。 此外，提供了定时特征库，存储介质的存储介质和使用存储介质的LSI设计方法的配置。

公开(公告)号：US20060101232A1

公开(公告)日：2006-05-11

申请号：US11240549

申请日：2005-10-03

申请人： Masashi Takada ,  Takanobu Tsunoda ,  Hiroshi Tanaka ,  Tetsuroo Honmura

发明人： Masashi Takada ,  Takanobu Tsunoda ,  Hiroshi Tanaka ,  Tetsuroo Honmura

IPC分类号： G06F15/00

CPC分类号： G06F9/3879 ,  G06F15/7867

摘要： The present invention relates to data access to a built-in memory or a peripheral circuit from any of ALU cells provided in the array state, and provides a semiconductor integrated circuit having an access mechanism enabling size reduction in the hardware scale and improvement in the usability. There are provided dedicated cell groups 1304, 1306 for executing memory access processing to built-in memories 1313, 1312 in a plurality of ALU cells. Further there are provided dedicated cell groups 1304, 1306 enabling access commonly available for built-in memories to a peripheral circuit 1201 or LSI external device 206. By providing dedicated cell groups for memory access processing to built-in memories, the ALU cell does not require a memory access mechanism, which enables reduction of an area and improvement in efficiency in use. Further access common to the built-in memories or peripheral circuits is possible, which enables improvement in the usability.

摘要翻译： 本发明涉及从阵列状态中提供的任何一个ALU单元到内置存储器或外围电路的数据访问，并且提供了一种半导体集成电路，其具有能够缩小硬件尺寸并提高可用性的访问机构 。 提供了用于对多个ALU单元中的内置存储器1313,1312执行存储器访问处理的专用单元组1304,1306。 此外，还提供了专用单元组1304,1306，使外部电路1201或LSI外部设备206的内置存储器通用。通过为内置存储器提供用于存储器访问处理的专用单元组，ALU单元不 需要存储器访问机制，这使得能够减少面积并提高使用效率。 内置存储器或外围电路通用的进一步访问是可能的，这样可以改善可用性。

公开(公告)号：US06845496B2

公开(公告)日：2005-01-18

申请号：US10173661

申请日：2002-06-19

申请人： Tetsuroo Honmura

发明人： Tetsuroo Honmura

IPC分类号： G06F1/32 ,  G06F11/22 ,  G06F11/28 ,  G06F15/78 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F15/7842 ,  G06F15/7867 ,  G06F17/5045 ,  Y02D10/13

摘要： A programmable peripheral LSI contains a number of microprocessor peripheral IPs. A switch is provided for selectively disabling peripheral IPs. As a result, the peripheral IPs are disabled while they are not used. An improved system design method uses an evaluation board provided with the programmable peripheral LSI.

摘要翻译： 可编程外设LSI包含多个微处理器外设IP。 提供用于选择性地禁用外围IP的开关。 因此，外围IP在不使用时被禁用。 改进的系统设计方法使用具有可编程外设LSI的评估板。

公开(公告)号：US07756505B2

公开(公告)日：2010-07-13

申请号：US11240618

申请日：2005-10-03

申请人： Hiroshi Tanaka ,  Takanobu Tsunoda ,  Tetsuroo Honmura ,  Manabu Kawabe ,  Masashi Takada

发明人： Hiroshi Tanaka ,  Takanobu Tsunoda ,  Tetsuroo Honmura ,  Manabu Kawabe ,  Masashi Takada

IPC分类号： H04B1/28 ,  H04B1/26 ,  H04M3/00 ,  H04M1/00 ,  G06F7/38 ,  G06F15/00 ,  G06F15/76 ,  G06F9/00 ,  G06F9/44 ,  H03K19/173 ,  H03K19/177 ,  H01L27/10 ,  H01L29/76

CPC分类号： H04B1/0003 ,  H04B1/406

摘要： To realize a software radio processing with a reduced circuit area by hardware and software which can process transmission and reception, or synchronization and demodulation in time division. There are provided a circuit DRC that can dynamically change a configuration with a structure that can change the configuration at a high speed, a general processor, and an interface for connection with an external device such as an AD converter or a DA converter. Software radio is realized by using a software radio chip that conducts plural different processing such as transmission and reception, or synchronization and demodulation in time division. The different processing during the radio signal processing can be conducted in time division. As a result, the software radio can be realized with a circuit of a reduced area in a software radio system that allocates regions of an FPGA to the respective processing.

摘要翻译： 通过可以处理发送和接收的硬件和软件实现具有减少电路面积的软件无线电处理，或者在时间上进行同步和解调。 提供了一种电路DRC，其可以以可以以高速度改变配置的结构动态地改变配置，通用处理器以及用于与诸如AD转换器或DA转换器的外部设备连接的接口。 软件无线电通过使用进行多个不同处理的软件无线电芯片来实现，例如发送和接收，或者时分的同步和解调。 无线电信号处理期间的不同处理可以分时进行。 结果，软件无线电可以通过在分配FPGA的区域到相应处理的软件无线电系统中的减小区域的电路来实现。

公开(公告)号：US20060073804A1

公开(公告)日：2006-04-06

申请号：US11240618

申请日：2005-10-03

申请人： Hiroshi Tanaka ,  Takanobu Tsunoda ,  Tetsuroo Honmura ,  Manabu Kawabe ,  Masashi Takada

发明人： Hiroshi Tanaka ,  Takanobu Tsunoda ,  Tetsuroo Honmura ,  Manabu Kawabe ,  Masashi Takada

IPC分类号： H04B1/28

CPC分类号： H04B1/0003 ,  H04B1/406

摘要： To realize a software radio processing with a reduced circuit area by hardware and software which can process transmission and reception, or synchronization and demodulation in time division. There are provided a circuit DRC that can dynamically change a configuration with a structure that can change the configuration at a high speed, a general processor, and an interface for connection with an external device such as an AD converter or a DA converter. Software radio is realized by using a software radio chip that conducts plural different processing such as transmission and reception, or synchronization and demodulation in time division. The different processing during the radio signal processing can be conducted in time division. As a result, the software radio can be realized with a circuit of a reduced area in a software radio system that allocates regions of an FPGA to the respective processing.

摘要翻译： 通过可以处理发送和接收的硬件和软件实现具有减少电路面积的软件无线电处理，或者在时间上进行同步和解调。 提供了一种电路DRC，其可以以可以以高速度改变配置的结构动态地改变配置，通用处理器和用于与诸如AD转换器或DA转换器的外部设备连接的接口。 软件无线电通过使用进行多个不同处理的软件无线电芯片来实现，例如发送和接收，或者时分的同步和解调。 无线电信号处理期间的不同处理可以分时进行。 结果，软件无线电可以通过在分配FPGA的区域到相应处理的软件无线电系统中的减小区域的电路来实现。

公开(公告)号：US07260669B2

公开(公告)日：2007-08-21

申请号：US10603797

申请日：2003-06-26

申请人： Tetsuroo Honmura

发明人： Tetsuroo Honmura

IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F12/0284 ,  H01L2924/0002 ,  H01L2924/00

摘要： When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus controller BSC makes address translation according to information on the relation between addresses of both memory spaces. The invention assures wider latitude in CPU type selection and makes it easy to reuse an existing program or develop a new program.

摘要翻译： 当外围LSI具有除了CPU的存储器空间之外的存储器空间时，进行访问，而没有其中一个存储空间知道其他存储空间。 灵活的总线控制器BSC根据关于两个存储空间地址之间的关系的信息进行地址转换。 本发明确保了CPU类型选择的更广泛的自由度，并且使得容易地重用现有的程序或开发新的程序。

公开(公告)号：US20070113231A1

公开(公告)日：2007-05-17

申请号：US11591612

申请日：2006-11-02

申请人： Tetsuroo Honmura

发明人： Tetsuroo Honmura

IPC分类号： G06F9/46

CPC分类号： G06F9/5066 ,  G06F9/4881 ,  G06F2209/483

摘要： A multi processor (107) includes a plurality of processor elements (103, 104, 105) and has a processing portion (210) capable of executing an application software and serving to carry out a process for determining a task to be assigned to the processor elements at a request given from the application software. The processing portion determines the task to be assigned to the processor elements at the request given from the application software. For task scheduling in the multi processor, consequently, it is possible to enhance a flexibility for an application software.

摘要翻译： 多处理器（107）包括多个处理器元件（103,104,105），并且具有能够执行应用软件并用于执行用于确定要分配给处理器的任务的处理的处理部分（210） 应用软件提供的请求元素。 处理部分根据应用软件给出的请求确定要分配给处理器元件的任务。 因此，对于多处理器中的任务调度，可以提高应用软件的灵活性。

公开(公告)号：US20060161314A1

公开(公告)日：2006-07-20

申请号：US11071366

申请日：2005-03-04

申请人： Tetsuroo Honmura

发明人： Tetsuroo Honmura

IPC分类号： G05D1/00

CPC分类号： G01C21/26 ,  G06F8/656

摘要： An automatic upgrading method in which, when software is downloaded and upgraded to change a specification of a software defined radio system on a vehicular system, convenience to a user who receives services using wireless communication is not reduced and error operations of the vehicular system is inhibited, is provided. A state in which a vehicle is not used is the most appropriate for the upgrade. It is determined whether a key is removed. When the key is removed, the download is executed using wireless communications. After that, a software defined radio system and a car navigation system are stopped. The upgrade and test operation are executed. When the test result is good, the software defined radio system and the car navigation system are restarted.

摘要翻译： 一种自动升级方法，其中当软件被下载和升级以改变车辆系统上的软件定义的无线电系统的规格时，对使用无线通信接收业务的用户的便利性不被降低，并且车辆系统的错误操作被禁止 ，被提供。 不使用车辆的状态是升级最合适的状态。 确定是否删除密钥。 当钥匙被移除时，使用无线通信执行下载。 之后，停止软件定义的无线电系统和汽车导航系统。 执行升级和测试操作。 当测试结果良好时，软件定义的无线电系统和汽车导航系统重启。