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1.发明申请Integrated Receiver and ADC for Capacitive Touch Sensing Apparatus and Methods 有权集成接收器和ADC用于电容式触摸感应装置和方法公开(公告)号：US20150130755A1
公开(公告)日：2015-05-14
申请号：US14531408
申请日：2014-11-03
Applicant: Texas Instruments Incorporated
Inventor： Karan Singh Jain , Harish Venkataraman , Susan Curtis
IPC: G06F3/044
CPC classification number: G06F3/044 , G06F3/0416
Abstract: An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.
Abstract translation: 一种用于电容式触摸屏的集成模拟数据接收器。 提供了一种用于触摸屏设备的模拟数据接收器电路，其包括被配置为直接连接到触摸屏设备的模拟输出的Σ-Δ模数转换器，并且还包括积分器电路，其具有被耦合用于接收模拟输出信号 并输出积分输出电压; 耦合到所述集成输出电压和第一偏置电压并输出比较电压的比较器; 耦合到比较电压和时钟信号的时钟采样锁存器，并输出与比较电压的采样相对应的量化数据位; 以及耦合到时钟采样锁存器的数字滤波器和抽取器，并且输出形成对应于触摸屏设备的输出的数字表示的串行数据位。 公开了附加电路和系统。
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公开(公告)号：US09916040B2
公开(公告)日：2018-03-13
申请号：US15369104
申请日：2016-12-05
Applicant: Texas Instruments Incorporated
Inventor： Karan Singh Jain , Harish Venkataraman
CPC classification number: G06F3/0418 , G06F3/044 , H03H11/11 , H03K17/962 , H03K2217/960735
Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.
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3.发明授权Method, apparatus and system for level shifting of common mode voltage from input to output for capacitive feedback transimpedance amplifier 有权用于电容反馈互阻抗放大器的共模电压从输入电平转换到输出的方法，装置和系统公开(公告)号：US09489098B2
公开(公告)日：2016-11-08
申请号：US14642602
申请日：2015-03-09
Applicant: Texas Instruments Incorporated
Inventor： Karan Singh Jain , Susan Ann Curtis , Harish Venkataraman
CPC classification number: G06F3/044 , G06F3/041 , G06F3/047 , G09G5/003 , G09G2300/0404 , H03F1/0205 , H03F3/45475 , H03F2200/135 , H03F2200/144 , H03F2200/555 , H03F2203/45101 , H03F2203/45138 , H03F2203/45526 , H03F2203/45528
Abstract: A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage source and another input of the first amplifier is coupled 2.5v, feedback resistor, Rfb, and feedback capacitor, Cfb, connected coupled to the voltage source, wherein other side of feedback resistor is coupled between two resistors, R2 and R2′, and wherein the other side of the feedback capacitor is coupled between R2′ and the output of the first amplifier, R2 is connected to Vbias from one side and Rfb and R2′ from the other, R2′ is connected to Rfb and R2 from one side and Cfb and output of the first amplifier from the other side, another resistor, R1, is connect to the output of the first amplifier, Cfb and R2′ from one side and R1′, yet another resistor, and input of amp2 from the other, a second amplifier, Amp2, is connected to the R1 and R1′ at one input and 1.5v at the other input, and wherein the output of the second amplifier is connected to R1′, and R1′ connects to one input of the second amplifier and the output of the second amplifier.
Abstract translation: 用于共模电压电平转换的电路。 电路包括第一放大器，其中第一放大器的输入耦合到电压源，并且第一放大器的另一输入耦合到2.5v，反馈电阻器Rfb和耦合到电压源的反馈电容器Cfb， 其中反馈电阻器的另一侧耦合在两个电阻器R2和R2'之间，并且其中反馈电容器的另一侧耦合在R2'和第一放大器的输出端之间，R2从一侧连接到Vbias，并且Rfb和 R2'从另一侧连接到Rfb和R2，Cfb和第一放大器的输出从另一侧连接，另一个电阻R1连接到第一放大器Cfb和R2'的输出 另一个电阻器和另一个的amp2的输入，第二放大器Amp2在一个输入处连接到R1和R1'，在另一个输入端连接到1.5v，并且其中第二个输出端 放大器连接到R1'和R1'c 连接到第二放大器的一个输入端和第二放大器的输出端。
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公开(公告)号：US09621304B2
公开(公告)日：2017-04-11
申请号：US14788147
申请日：2015-06-30
Applicant: Texas Instruments Incorporated
Inventor： Gary Franklin Chard , Erick Omar Torres , Karan Singh Jain
CPC classification number: H04L1/0046 , H03M5/12 , H03M13/151 , H04L25/4904
Abstract: A method of decoding a biphase mark coded (BMC) data stream. A BMC encoded signal (BMC signal) including a preamble and data payload is received at a receiver which includes a BMC decoder state machine (state machine). The preamble is processed using the state machine including measuring a total duration spanning at least three transitions to provide a ≧2 UI duration measure, a calculated 0.75 UI duration value (0.75 UI duration value) is generated from the ≧2 UI duration measure, and the 0.75 UI duration value is compared to a programmed UI range. Provided the 0.75 UI duration value is within the programmed UI range data, respective bits are extracted bit-by-bit from the data payload using the 0.75 UI duration value to obtain unencoded data.
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公开(公告)号：US20170083161A1
公开(公告)日：2017-03-23
申请号：US15369104
申请日：2016-12-05
Applicant: Texas Instruments Incorporated
Inventor： Karan Singh Jain , Harish Venkataraman
CPC classification number: G06F3/0418 , G06F3/044 , H03H11/11 , H03K17/962 , H03K2217/960735
Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.
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Patent Agency Ranking
公开(公告)号：US20150130434A1
公开(公告)日：2015-05-14
申请号：US14446563
申请日：2014-07-30
Applicant: Texas Instruments Incorporated
Inventor： Karan Singh Jain , Timothy Bryan Merkin , Susan Curtis
IPC: G05F1/575
Abstract: A circuit and method for providing a current limiting feature in a low dropout (“LDO”) linear voltage regulator. A pass element generates an output voltage that is less than the input voltage. The pass element is normally enabled by an error amplifier that compares a feedback signal from the output of the pass element with a reference signal. However, the pass element may be enabled by a current limiting circuit that bypasses the error amplifier to limit the current generated at the output of the pass element.
Abstract translation: 一种用于在低压差（“LDO”）线性稳压器中提供限流特性的电路和方法。 传递元件产生小于输入电压的输出电压。 通过元件通常由误差放大器使能，该误差放大器将来自通过元件的输出的反馈信号与参考信号进行比较。 然而，通过元件可以通过旁路误差放大器的限流电路使能，以限制在通过元件的输出处产生的电流。
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公开(公告)号：US09535439B2
公开(公告)日：2017-01-03
申请号：US14446563
申请日：2014-07-30
Applicant: Texas Instruments Incorporated
Inventor： Karan Singh Jain , Timothy Bryan Merkin , Susan Curtis
Abstract: A circuit and method for providing a current limiting feature in a low dropout (“LDO”) linear voltage regulator. A pass element generates an output voltage that is less than the input voltage. The pass element is normally enabled by an error amplifier that compares a feedback signal from the output of the pass element with a reference signal. However, the pass element may be enabled by a current limiting circuit that bypasses the error amplifier to limit the current generated at the output of the pass element.
Abstract translation: 一种用于在低压差（“LDO”）线性稳压器中提供限流特性的电路和方法。 传递元件产生小于输入电压的输出电压。 通过元件通常由误差放大器使能，该误差放大器将来自通过元件的输出的反馈信号与参考信号进行比较。 然而，通过元件可以通过旁路误差放大器的限流电路使能，以限制在通过元件的输出处产生的电流。
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公开(公告)号：US09513741B2
公开(公告)日：2016-12-06
申请号：US13973049
申请日：2013-08-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Karan Singh Jain , Harish Venkataraman
CPC classification number: G06F3/0418 , G06F3/044 , H03H11/11 , H03K17/962 , H03K2217/960735
Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.
Abstract translation: 公开了一种带通读出放大器电路（图2A）。 电路包括具有耦合以接收输入信号（Vin）和第二端子的第一端子的电容器（C0）。 目前的输送机电路（200-206,212）具有耦合到电容器的第二端子的第三端子（X）和布置成将电流镜像到第三端子中的第四端子（Z）。 电压跟随器电路（214）具有耦合到当前输送电路的第四端子的输入端子和输出端子。
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9.发明授权Integrated receiver and ADC for capacitive touch sensing apparatus and methods 有权集成接收器和ADC用于电容式触摸传感设备和方法公开(公告)号：US09256335B2
公开(公告)日：2016-02-09
申请号：US14531408
申请日：2014-11-03
Applicant: Texas Instruments Incorporated
Inventor： Karan Singh Jain , Harish Venkataraman , Susan Curtis
CPC classification number: G06F3/044 , G06F3/0416
Abstract: An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.
Abstract translation: 一种用于电容式触摸屏的集成模拟数据接收器。 提供了一种用于触摸屏设备的模拟数据接收器电路，其包括被配置为直接连接到触摸屏设备的模拟输出的Σ-Δ模数转换器，并且还包括积分器电路，其具有被耦合用于接收模拟输出信号 并输出积分输出电压; 耦合到所述集成输出电压和第一偏置电压并输出比较电压的比较器; 耦合到比较电压和时钟信号的时钟采样锁存器，并输出与比较电压的采样相对应的量化数据位; 以及耦合到时钟采样锁存器的数字滤波器和抽取器，并且输出形成对应于触摸屏设备的输出的数字表示的串行数据位。 公开了附加电路和系统。
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10.发明申请公开(公告)号：US20150256136A1
公开(公告)日：2015-09-10
申请号：US14642602
申请日：2015-03-09
Applicant: Texas Instruments Incorporated
Inventor： Karan Singh Jain , Susan Ann Curtis , Harish Venkataraman
CPC classification number: G06F3/044 , G06F3/041 , G06F3/047 , G09G5/003 , G09G2300/0404 , H03F1/0205 , H03F3/45475 , H03F2200/135 , H03F2200/144 , H03F2200/555 , H03F2203/45101 , H03F2203/45138 , H03F2203/45526 , H03F2203/45528
Abstract: A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage source and another input of the first amplifier is coupled 2.5v, feedback resistor, Rfb, and feedback capacitor, Cfb, connected coupled to the voltage source, wherein other side of feedback resistor is coupled between two resistors, R2 and R2′, and wherein the other side of the feedback capacitor is coupled between R2′ and the output of the first amplifier, R2 is connected to Vbias from one side and Rfb and R2′ from the other, R2′ is connected to Rfb and R2 from one side and Cfb and output of the first amplifier from the other side, another resistor, R1, is connect to the output of the first amplifier, Cfb and R2′ from one side and R1′, yet another resistor, and input of amp2 from the other, a second amplifier, Amp2, is connected to the R1 and R1′ at one input and 1.5v at the other input, and wherein the output of the second amplifier is connected to R1′, and R1′ connects to one input of the second amplifier and the output of the second amplifier.
Abstract translation: 用于共模电压电平转换的电路。 电路包括第一放大器，其中第一放大器的输入耦合到电压源，并且第一放大器的另一输入耦合到2.5v，反馈电阻器Rfb和耦合到电压源的反馈电容器Cfb， 其中反馈电阻器的另一侧耦合在两个电阻器R2和R2'之间，并且其中反馈电容器的另一侧耦合在R2'和第一放大器的输出端之间，R2从一侧连接到Vbias，并且Rfb和 R2'从另一侧连接到Rfb和R2，Cfb和第一放大器的输出从另一侧连接，另一个电阻R1连接到第一放大器Cfb和R2'的输出 另一个电阻器和另一个的amp2的输入，第二放大器Amp2在一个输入处连接到R1和R1'，在另一个输入端连接到1.5v，并且其中第二个输出端 放大器连接到R1'和R1'c 连接到第二放大器的一个输入端和第二放大器的输出端。
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