公开(公告)号：US20150213883A1

公开(公告)日：2015-07-30

申请号：US14679644

申请日：2015-04-06

Applicant: Texas Instruments Incorporated

Inventor： Srinivasa Raghavan Sridhara

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/41 ,  G11C29/50012

Abstract: An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected. A binary logical value is written to a memory cell in the SRAM. The single dummy word line and a word line containing the memory cell in the SRAM are driven to logical high values concurrently. A dummy bit line, driven by the dummy memory cells, drives an input of a buffer to a binary logical value stored in the dummy memory cells. An output of the buffer enables a sense amp to amplify a voltage developed across the bit lines electrically connected to the memory cell.

Abstract translation: 本发明的实施例公开了一种用于测试SRAM中的存储单元的方法。 选择用于驱动虚拟位线的单个虚拟字线上的虚拟存储器单元的数量。 二进制逻辑值被写入SRAM中的存储单元。 单个虚拟字线和包含SRAM中的存储单元的字线被并行地驱动到逻辑高值。 由虚拟存储器单元驱动的虚拟位线将缓冲器的输入驱动到存储在虚拟存储单元中的二进制逻辑值。 缓冲器的输出使得读出放大器放大电连接到存储单元的位线之间产生的电压。

公开(公告)号：US09496024B1

公开(公告)日：2016-11-15

申请号：US14974945

申请日：2015-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivasa Raghavan Sridhara ,  Sanjeev Kumar Suman ,  Premkumar Seetharaman ,  Keshav Bhaktavatson Chintamani ,  Atul Ramakant Lele ,  Raviprakash S. Rao ,  Parvinder Kumar Rana ,  Ajith Subramonia ,  Vipul K. Singhal ,  Malav Shrikant Shah ,  Bharath Kumar Poluri

IPC: G11C5/14 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C11/413

Abstract: A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Abstract translation: 芯片上的系统（SOC）包括处理器和耦合到处理器的存储器系统。 存储器系统包括静态随机存取存储器（SRAM）存储体和存储器控制器。 SRAM库包括耦合到SRAM阵列电源的第一开关和SRAM阵列中的SRAM存储单元的晶体管的源极。 SRAM库还包括耦合到NWELL电源和SRAM存储单元的大部分晶体管的第二开关。 第二开关被配置为在SRAM阵列上电期间在第一开关闭合之前关闭。

公开(公告)号：US09646680B2

公开(公告)日：2017-05-09

申请号：US15060150

申请日：2016-03-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivasa Raghavan Sridhara

IPC: G11C11/40 ,  G11C11/417 ,  G11C5/14 ,  G11C11/412 ,  G11C11/4074

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412

Abstract: In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.

公开(公告)号：US09311989B2

公开(公告)日：2016-04-12

申请号：US14331648

申请日：2014-07-15

Applicant: Texas Instruments Incorporated

Inventor： Srinivasa Raghavan Sridhara

IPC: G11C11/40 ,  G11C11/417 ,  G11C11/412 ,  G11C5/14

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412

Abstract: In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.

Abstract translation: 在本发明的一个实施例中，通过以大致相同的速率对SRAM阵列中的正电压节点和SRAM中的Nwell区域充电而将电力提供给SRAM阵列而不引起闩锁。

公开(公告)号：US20160019945A1

公开(公告)日：2016-01-21

申请号：US14331648

申请日：2014-07-15

Applicant: Texas Instruments Incorporated

Inventor： Srinivasa Raghavan Sridhara

IPC: G11C11/417 ,  G11C5/14 ,  G11C11/412

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412

Abstract: In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.

Abstract translation: 在本发明的一个实施例中，通过以大致相同的速率对SRAM阵列中的正电压节点和SRAM中的Nwell区域充电而将电力提供给SRAM阵列而不引起闩锁。

公开(公告)号：US20160189768A1

公开(公告)日：2016-06-30

申请号：US15060150

申请日：2016-03-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivasa Raghavan Sridhara

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412

Abstract: In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.

Abstract translation: 在本发明的一个实施例中，通过以大致相同的速率对SRAM阵列中的正电压节点和SRAM中的Nwell区域充电而将电力提供给SRAM阵列而不引起闩锁。