公开(公告)号：US20220416014A1

公开(公告)日：2022-12-29

申请号：US17512484

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K. Jain

IPC: H01L49/02

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US20190296115A1

公开(公告)日：2019-09-26

申请号：US16042834

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US12080755B2

公开(公告)日：2024-09-03

申请号：US17512484

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K Jain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/495 ,  H01L27/08 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US11322594B2

公开(公告)日：2022-05-03

申请号：US17134706

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Fei Ma ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Baoqiang Niu ,  Rui Liu ,  Zhi Peng Feng ,  Seetharaman Sridhar ,  Sunglyong Kim

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/765 ,  H01L29/423 ,  H01L27/24 ,  H01L21/8234

Abstract: A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.

公开(公告)号：US20240395854A1

公开(公告)日：2024-11-28

申请号：US18795747

申请日：2024-08-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K Jain

IPC: H01G4/30

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US20200335589A1

公开(公告)日：2020-10-22

申请号：US16918130

申请日：2020-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US10720499B2

公开(公告)日：2020-07-21

申请号：US16042834

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.