Abstract:
A switching technique allows multiple interconnect bus devices to be connected to a single bus segment, even if the interconnect bus protocol only allows a one of the interconnect devices to be connected at any time. Each of the interconnect devices is connected to the interconnect bus segment with a switch, such that the interconnect device is electrically isolated from the interconnect bus segment when the switch is open. An interconnect sourcing agent connected to the interconnect bus segment controls the switches, closing the switch for one of the interconnect devices when a transaction is destined for that interconnect device, opening all of the other switches so that only one device is connected to the bus at any time.
Abstract:
A stack of interleaved towels is provided wherein each towel is configured from a sheet of material having a first fold offset from a centerline of the sheet to generate a folded sheet having a long side and a short side. A second fold in the folded sheet is made substantially parallel to the first fold to create a lead flap and a trailing flap. The lead flap presents a continuous folded leading edge for grasping by a user. The trailing flap is defined between the second fold and edges of the long side and short side. The trailing flap of each towel is disposed against the lead flap of an adjacent towel. In the stack, the short side of the trailing flap is disposed so that it is facing upwards upon a user grasping the lead flap and pulling the towel from a dispenser.
Abstract:
In a first aspect, a method of forming a memory cell is provided that includes: (a) forming a layer of dielectric material above a substrate; (b) forming an opening in the dielectric layer; (c) depositing a solution that includes a carbon-based switching material on the substrate; (d) rotating the substrate to cause the solution to flow into the opening and to form a carbon-based switching material layer within the opening; and (e) forming a memory element using the carbon-based switching material layer. Numerous other aspects are provided.
Abstract:
The present invention relates to the placement of signal traces on a two-sided printed circuit board such that impedance of the traces is controlled and so that the number of power and ground pins required on an integrated circuit are minimized.
Abstract:
The present invention relates to the placement of signal traces on a two-sided printed circuit board such that impedance of the traces is controlled and so that the number of power and ground pins required on an integrated circuit are minimized.