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公开(公告)号：US5249266A
公开(公告)日：1993-09-28
申请号：US865003
申请日：1992-04-08
申请人： Thomas A. Dye , Derek Roskell , Richard Simpson , Michael D. Asal , Karl M. Guttag , Neil Tebbutt , Jerry R. Van Aken
发明人： Thomas A. Dye , Derek Roskell , Richard Simpson , Michael D. Asal , Karl M. Guttag , Neil Tebbutt , Jerry R. Van Aken
CPC分类号： G06F9/30043 , G06F9/455 , G06T1/20
摘要： A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user. Similarly, responsive instead to a load command, a routine is executed which presents the series of addresses to the memory bus and loads the internal registers with the data values presented on the memory bus. The load feature is similarly utilized by the user's loading of the addressed memory locations with the desired contents of the internal registers. A system containing a microprocessor constructed according to the invention may be configured so that the emulate enable signal is generated by the control signals generated by the microprocessor upon each instruction fetch from the external memory.
摘要翻译： 一种特别适用于图形处理应用的微处理器，其具有自我仿真功能，通过该自动仿真功能，内部寄存器的内容可以在逐个指令的基础上被转储或从外部存储器加载到外部存储器。 微处理器具有对仿真使能信号或预定指令代码作出响应的电路，使得在离子的末端停止正常执行，执行跳转到预定向量。 响应于转储信号，微处理器开始执行程序，其结合存储器总线内部的寄存器内容，在存储器总线上呈现预定的一系列存储器地址。 因此，连接到存储器总线的存储器件的寻址位置可以用寄存器内容写入，以供用户的后续询问。 类似地，响应于负载命令，执行向存储器总线提供一系列地址的例程，并且使用存储器总线上呈现的数据值加载内部寄存器。 负载特征类似地由用户使用内部寄存器的期望内容加载寻址的存储器位置。 可以配置包含根据本发明构造的微处理器的系统，使得在从外部存储器提取每次指令时由微处理器产生的控制信号产生仿真使能信号。
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公开(公告)号：US5140687A
公开(公告)日：1992-08-18
申请号：US415375
申请日：1989-09-27
申请人： Thomas A. Dye , Derek Roskell , Richard Simpson , Michael Asal , Karl M. Guttag , Neil Tebbutt , Jerry Van Aken
发明人： Thomas A. Dye , Derek Roskell , Richard Simpson , Michael Asal , Karl M. Guttag , Neil Tebbutt , Jerry Van Aken
CPC分类号： G06F9/30043 , G06F9/455 , G06T1/20
摘要： A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user. Similarly, responsive instead to a load command, a routine is executed which presents the series of addresses to the memory bus and loads the internal registers with the data values presented on the memory bus. The load feature is similarly utilized by the user's loading of the addressed memory locations with the desired contents of the internal registers. A system containing a microprocessor constructed according to the invention may be configured so that the emulate enable signal is generated by the control signals generated by the microprocessor upon each instruction fetch from the external memory.
摘要翻译： 一种特别适用于图形处理应用的微处理器，其具有自我仿真功能，通过该自动仿真功能，内部寄存器的内容可以在逐个指令的基础上被转储或从外部存储器加载到外部存储器。 微处理器具有对仿真使能信号或预定指令代码作出响应的电路，使得在离子的末端停止正常执行，执行跳转到预定向量。 响应于转储信号，微处理器开始执行程序，其结合存储器总线内部的寄存器内容，在存储器总线上呈现预定的一系列存储器地址。 因此，连接到存储器总线的存储器件的寻址位置可以用寄存器内容写入，以供用户的后续询问。 类似地，响应于负载命令，执行向存储器总线提供一系列地址的例程，并且使用存储器总线上呈现的数据值加载内部寄存器。 负载特征类似地由用户使用内部寄存器的期望内容加载寻址的存储器位置。 可以配置包含根据本发明构造的微处理器的系统，使得在从外部存储器提取每次指令时由微处理器产生的控制信号产生仿真使能信号。
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公开(公告)号：US5923340A
公开(公告)日：1999-07-13
申请号：US485540
申请日：1995-06-07
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may by simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译： 本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。 第一数据寄存器存储一组X和Y坐标。 在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。 然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。 第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。 预定的颜色代码优选地存储在另一个数据寄存器中。 通过适当选择存储在第二数据寄存器中的X和Y坐标数据，X或Y坐标可以单独改变，或者两者可以同时改变。 在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。 该指令用于提高在位映射显示中绘制线或计算曲线的速度。
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4.发明授权Graphics computer system, a graphics system arrangement, a display system, a graphics processor and a method of processing graphic data 失效图形计算机系统，图形系统布置，显示系统，图形处理器和处理图形数据的方法
公开(公告)号：US5437011A
公开(公告)日：1995-07-25
申请号：US191885
申请日：1994-02-04
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored In a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first data register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented or decremented. This instruction serves to enhance the speed at which a line or computed curve may be drawn in the bit mapped display.
摘要翻译： 本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。 第一数据寄存器存储一组X和Y坐标。 在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。 然后，存储在第一数据寄存器中的X和Y坐标通过添加存储在第二数据寄存器中的X和Y坐标来提前。 第二实施例是类似的，除了存储在第一数据寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。 预定的颜色代码优选地存储在另一个数据寄存器中。 通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。 在第二个寄存器中提供有符号的X和Y坐标值可使X或Y坐标值递增或递减。 该指令用于增强在位映射显示中绘制线或计算曲线的速度。
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公开(公告)号：US5162784A
公开(公告)日：1992-11-10
申请号：US522409
申请日：1990-05-10
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to enhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译： 本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。 第一数据寄存器存储一组X和Y坐标。 在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。 然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。 第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。 预定的颜色代码优选地存储在另一个数据寄存器中。 通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。 在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。 该指令用于提高在位映射显示中绘制线或计算曲线的速度。
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公开(公告)号：US5317333A
公开(公告)日：1994-05-31
申请号：US916302
申请日：1992-07-17
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译： 本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。 第一数据寄存器存储一组X和Y坐标。 在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。 然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。 第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。 预定的颜色代码优选地存储在另一个数据寄存器中。 通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。 在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。 该指令用于提高在位映射显示中绘制线或计算曲线的速度。
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7.发明授权Graphics systems, palettes and methods with combined video and shift clock control 失效图形系统，调色板和具有组合视频和移位时钟控制的方法
公开(公告)号：US5287100A
公开(公告)日：1994-02-15
申请号：US545424
申请日：1990-06-27
申请人： Karl M. Guttag , Jeffrey L. Nye , Jerry R. Van Aken , Carrell R. Killebrew, Jr. , Michael D. Asal
发明人： Karl M. Guttag , Jeffrey L. Nye , Jerry R. Van Aken , Carrell R. Killebrew, Jr. , Michael D. Asal
CPC分类号： G09G5/363 , G09G5/06 , G09G5/12 , G09G5/39 , G09G2330/12 , G09G2360/02 , G09G2360/123 , G09G5/022
摘要： An integrated circuit for use with a plurality of clock oscillators. The integrated circuit has a semiconductor chip, function performing circuitry fabricated on the semiconductor chip and responsive to clock pulses provided thereto, and a semiconductor chip package having pins connected to the function performing circuitry. The integrated circuit further has a register accessible via the pins for external entry of clock control information. A clock control circuit responsive to the clock control information entered in said register has inputs connected to pins for the clock oscillators. The function performing circuitry is connected to the clock control circuit so that clock pulses are provided to the function performing circuitry by the clock control circuit in accordance with the clock control information entered in the register. Other integrated circuits, palette devices, computer graphics systems, printer systems and methods are also disclosed.
摘要翻译： 一种用于多个时钟振荡器的集成电路。 集成电路具有半导体芯片，功能执行电路，其制造在半导体芯片上并响应提供给其的时钟脉冲，以及具有连接到功能执行电路的引脚的半导体芯片封装。 集成电路还具有可通过引脚访问的寄存器，用于外部输入时钟控制信息。 响应于在所述寄存器中输入的时钟控制信息的时钟控制电路具有连接到时钟振荡器的引脚的输入。 功能执行电路连接到时钟控制电路，使得时钟脉冲根据输入到寄存器中的时钟控制信息由时钟控制电路提供给功能执行电路。 还公开了其他集成电路，调色板装置，计算机图形系统，打印机系统和方法。
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8.发明授权Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers 失效具有分别在像素位置寄存器的X和Y坐标上操作的指令的图形处理装置
公开(公告)号：US5142621A
公开(公告)日：1992-08-25
申请号：US498457
申请日：1990-03-21
申请人： Karl M. Guttag , Michael D. Asal , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Neil Tebbutt , Mark F. Novak
CPC分类号： G06T1/20 , G06F15/7857 , G06F9/345 , G06F9/3885
摘要： The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.
摘要翻译： 本发明的图形处理装置利用寄存器文件的各个寄存器来存储像素的X和Y坐标。 这些X和Y坐标虽然形成单个数据字，但是可以通过例如具有指定Y坐标的最高有效位和指定Y坐标的最低有效位来分离。 图形处理装置支持提供对这些X和Y坐标的单独且独立的数据操纵的指令。 这些X Y坐标操作指令可以为两个数据字提供单独的X Y算术运算，分别进行X和Y比较运算，单独的X和Y数据移动操作以及X Y地址格式与线性地址格式之间的转换。 该技术对于使用位映射图形的可视显示系统中的X Y地址坐标的操纵非常有用。
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9.发明授权Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers 失效具有分别在像素位置寄存器的X和Y坐标上操作的指令的图形处理装置
公开(公告)号：US5333261A
公开(公告)日：1994-07-26
申请号：US59006
申请日：1993-05-07
申请人： Karl M. Guttag , Michael D. Asal , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Neil Tebbutt , Mark F. Novak
CPC分类号： G06F9/345 , G06F15/7857 , G06F9/3885 , G06T1/20
摘要： The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.
摘要翻译： 本发明的图形处理装置利用寄存器文件的各个寄存器来存储像素的X和Y坐标。 这些X和Y坐标虽然形成单个数据字，但是可以通过例如具有指定Y坐标的最高有效位和指定Y坐标的最低有效位来分离。 图形处理装置支持提供对这些X和Y坐标的单独且独立的数据操纵的指令。 这些X Y坐标操作指令可以为两个数据字提供单独的X Y算术运算，分别进行X和Y比较运算，单独的X和Y数据移动操作以及X Y地址格式与线性地址格式之间的转换。 该技术对于使用位映射图形的可视显示系统中的X Y地址坐标的操纵非常有用。
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10.发明授权Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR 失效迭代分割装置，采用最左侧检测的系统和方法，最大限度地利用异或进行检测
公开(公告)号：US5596519A
公开(公告)日：1997-01-21
申请号：US484113
申请日：1995-06-07
CPC分类号： G06F7/74 , G06F7/535 , G06F2207/5353 , G06F7/49936
摘要： An iterative technique for division having a divisor of N bits and a numerator of more than N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator is left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. Next the divisor is subtracted from the N most significant bits of the numerator. If the difference is greater than or equal to zero, then the next quotient bit is "1" and the difference is substituted for the N most significant bits of the numerator. If the difference is less than zero, then the next quotient bit is "0". Then the numerator is left shifted one place. These iterations repeat until they exceed N. The last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are "0".
摘要翻译： 一种用于除法的迭代技术，其具有N位的除数和大于N位的分子。 每个迭代包括对分子的N个最高有效位的最左一位（1011,1035）的位置的初始检测。 如果该L不为零，则分子左移L位（1016,1033），下一个L商位被设置为零，并且完成的迭代次数增加L.替代实施例检测位置 留下分子和除数的N个最高有效位的异或的最多的一个。 接下来，从分子的N个最高有效位中减去除数。 如果差值大于或等于零，则下一个商位为“1”，差值代替分子的N个最高有效位。 如果差值小于零，则下一个商位为“0”。 然后分子左移一个位置。 这些迭代重复直到它们超过N.最后一个分子是除法的剩余部分。 这种技术消除了这种技术确定商位为“0”的情况下的无用数据操作。
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