公开(公告)号：US5249266A

公开(公告)日：1993-09-28

申请号：US865003

申请日：1992-04-08

申请人： Thomas A. Dye ,  Derek Roskell ,  Richard Simpson ,  Michael D. Asal ,  Karl M. Guttag ,  Neil Tebbutt ,  Jerry R. Van Aken

发明人： Thomas A. Dye ,  Derek Roskell ,  Richard Simpson ,  Michael D. Asal ,  Karl M. Guttag ,  Neil Tebbutt ,  Jerry R. Van Aken

IPC分类号： G06F9/312 ,  G06F9/455 ,  G06T1/20

CPC分类号： G06F9/30043 ,  G06F9/455 ,  G06T1/20

摘要： A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user. Similarly, responsive instead to a load command, a routine is executed which presents the series of addresses to the memory bus and loads the internal registers with the data values presented on the memory bus. The load feature is similarly utilized by the user's loading of the addressed memory locations with the desired contents of the internal registers. A system containing a microprocessor constructed according to the invention may be configured so that the emulate enable signal is generated by the control signals generated by the microprocessor upon each instruction fetch from the external memory.

摘要翻译： 一种特别适用于图形处理应用的微处理器，其具有自我仿真功能，通过该自动仿真功能，内部寄存器的内容可以在逐个指令的基础上被转储或从外部存储器加载到外部存储器。 微处理器具有对仿真使能信号或预定指令代码作出响应的电路，使得在离子的末端停止正常执行，执行跳转到预定向量。 响应于转储信号，微处理器开始执行程序，其结合存储器总线内部的寄存器内容，在存储器总线上呈现预定的一系列存储器地址。 因此，连接到存储器总线的存储器件的寻址位置可以用寄存器内容写入，以供用户的后续询问。 类似地，响应于负载命令，执行向存储器总线提供一系列地址的例程，并且使用存储器总线上呈现的数据值加载内部寄存器。 负载特征类似地由用户使用内部寄存器的期望内容加载寻址的存储器位置。 可以配置包含根据本发明构造的微处理器的系统，使得在从外部存储器提取每次指令时由微处理器产生的控制信号产生仿真使能信号。

公开(公告)号：US5140687A

公开(公告)日：1992-08-18

申请号：US415375

申请日：1989-09-27

申请人： Thomas A. Dye ,  Derek Roskell ,  Richard Simpson ,  Michael Asal ,  Karl M. Guttag ,  Neil Tebbutt ,  Jerry Van Aken

发明人： Thomas A. Dye ,  Derek Roskell ,  Richard Simpson ,  Michael Asal ,  Karl M. Guttag ,  Neil Tebbutt ,  Jerry Van Aken

IPC分类号： G06F9/312 ,  G06F9/455 ,  G06T1/20

CPC分类号： G06F9/30043 ,  G06F9/455 ,  G06T1/20

摘要： A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user. Similarly, responsive instead to a load command, a routine is executed which presents the series of addresses to the memory bus and loads the internal registers with the data values presented on the memory bus. The load feature is similarly utilized by the user's loading of the addressed memory locations with the desired contents of the internal registers. A system containing a microprocessor constructed according to the invention may be configured so that the emulate enable signal is generated by the control signals generated by the microprocessor upon each instruction fetch from the external memory.

摘要翻译： 一种特别适用于图形处理应用的微处理器，其具有自我仿真功能，通过该自动仿真功能，内部寄存器的内容可以在逐个指令的基础上被转储或从外部存储器加载到外部存储器。 微处理器具有对仿真使能信号或预定指令代码作出响应的电路，使得在离子的末端停止正常执行，执行跳转到预定向量。 响应于转储信号，微处理器开始执行程序，其结合存储器总线内部的寄存器内容，在存储器总线上呈现预定的一系列存储器地址。 因此，连接到存储器总线的存储器件的寻址位置可以用寄存器内容写入，以供用户的后续询问。 类似地，响应于负载命令，执行向存储器总线提供一系列地址的例程，并且使用存储器总线上呈现的数据值加载内部寄存器。 负载特征类似地由用户使用内部寄存器的期望内容加载寻址的存储器位置。 可以配置包含根据本发明构造的微处理器的系统，使得在从外部存储器提取每次指令时由微处理器产生的控制信号产生仿真使能信号。

公开(公告)号：US5371517A

公开(公告)日：1994-12-06

申请号：US791757

申请日：1991-11-08

申请人： Louis Izzi ,  William R. Krenik ,  Henry T. Yung ,  Chenwei J. Yin ,  Carrell R. Killebrew, Jr. ,  Karl Guttag ,  Jerry R. Van Aken ,  Jeffrey Nye ,  Richard Simpson ,  Mike Asal

发明人： Louis Izzi ,  William R. Krenik ,  Henry T. Yung ,  Chenwei J. Yin ,  Carrell R. Killebrew, Jr. ,  Karl Guttag ,  Jerry R. Van Aken ,  Jeffrey Nye ,  Richard Simpson ,  Mike Asal

IPC分类号： G06F11/00 ,  G09G5/06 ,  G09G5/18 ,  G09G1/28

CPC分类号： G06F11/006 ,  G09G5/06 ,  G09G5/18

摘要： A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.

摘要翻译： 响应于在控制数据终端接收的主时钟选择控制字，调色板从在时钟输入端接收的多个时钟信号中选择主时钟。 A电路根据主时钟的选择的分频比形成多个分频的下降时钟信号。 电路响应于在控制数据端子处接收的输出时钟选择控制字的至少一些位，从分频的下降时钟信号中选择移位时钟。 电路响应于消隐数据选择性地启用和禁用移位时钟。 响应于输出时钟选择控制字的至少一些位，电路从分频的下降时钟信号中选择视频时钟。 电路将彩色码输入端子接收的彩色码的多位字与主时钟同步。 响应于接收到颜色代码的每个多个位字，A电路输出至少一个存储器调用地址。 电路将颜色数据字存储在具有相关联的存储器调用地址的多个数据存储位置中，并且在接收到相关联的存储器调用地址时输出彩色数据字。 电路将彩色数据字选择性地写入这些多个位置。 电路将视频控制终端接收的视频控制信号与主时钟同步，并提供消隐数据。 电路选择所述颜色数据字和在所述颜色代码输入端接收的真彩色数据字之间的输出。

公开(公告)号：US5596763A

公开(公告)日：1997-01-21

申请号：US159285

申请日：1993-11-30

申请人： Karl M. Guttag ,  Richard Simpson ,  Brendan Walsh

发明人： Karl M. Guttag ,  Richard Simpson ,  Brendan Walsh

IPC分类号： G06F7/00 ,  G06F7/57 ,  G06F7/575 ,  G06F12/08 ,  G06T1/20 ,  G06F7/38 ,  G06F7/50

CPC分类号： G06F7/575 ,  G06F2207/382 ,  G06F7/49994

摘要： A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals may employed with a multilevel logic tree circuit and a carry input to produce a bit resultant and a carry output to the next bit circuit. This structure permits formation of selected arithmetic, Boolean or mixed arithmetic and Boolean function of the three input signals based upon the current instruction. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performs a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use. The three input arithmetic logic unit (230) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is "1" only during subtraction. The carry input may be specified in the special purpose data register (D0) for certain instructions. The combination formed is optionally modified dependent upon the sign bit of one of the inputs.

摘要翻译： 三输入算术逻辑单元（230）形成三个多位输入信号的混合运算和布尔组合。 算术逻辑单元（230）首先形成布尔组合，然后形成算术组合。 当前指令驱动产生控制所形成的组合的功能信号F0-F7的指令译码器（250,245）。 三输入算术逻辑单元（230）优选地采用一组比特电路（400），每一组形成进位传播，产生和终止信号。 这些信号可以与多级逻辑树电路和进位输入一起使用，以产生位结果和进位输出到下一位电路。 该结构允许基于当前指令形成三个输入信号的所选算术，布尔或混合运算和布尔函数。 功能信号的选择使得组合对输入信号之一不敏感，从而执行剩余输入信号的两个输入功能。 指令本身可以包括功能信号和功能修改位，或者功能信号和功能修改信号可以存储在特殊数据寄存器中。 功能修改信号在使用前会引起功能信号的修改。 三输入算术逻辑单元（230）包括向最低有效位提供进位输入的最低有效位进位发生器（246）。 该进位输入由形成的组合确定，并且通常在减法期间为“1”。 某些指令可以在专用数据寄存器（D0）中指定进位输入。 根据其中一个输入的符号位可选地修改形成的组合。

公开(公告)号：US5537563A

公开(公告)日：1996-07-16

申请号：US018487

申请日：1993-02-16

申请人： Karl M. Guttag ,  Robert J. Gove ,  Richard Simpson

发明人： Karl M. Guttag ,  Robert J. Gove ,  Richard Simpson

IPC分类号： G09G5/39 ,  G06F13/00

CPC分类号： G09G5/39 ,  G09G2352/00

摘要： A processing system operates on data words each having first and second portions. A first memory stores the first portion of a first data word accessible by a first set of address bits received at first address inputs and a second set of address bits received at second address inputs, and stores the second portion of a second word accessible by the first set of address bits received at the first address inputs and a third set of address bits received at the second address inputs. A second memory stores the first portion of the second data word accessible by a first set of address bits received at first address inputs and a second set of bits received at second address input, and stores the second portion of the first word accessible by the first set of address bits received at the first address inputs and a third set of address bits received at the second address inputs. A first access mode accesses a selected one of the first and second portions of both the first and second words. A second access mode accesses both the first and second portions of a selected one of the first and second words.

摘要翻译： 处理系统对每个具有第一和第二部分的数据字进行操作。 第一存储器存储由在第一地址输入处接收的第一组地址位可访问的第一数据字的第一部分和在第二地址输入处接收的第二组地址位，并且存储由第二地址位可访问的第二字的第二部分 在第一地址输入处接收的第一组地址位和在第二地址输入处接收的第三组地址位。 第二存储器存储由在第一地址输入处接收的第一组地址位可访问的第二数据字的第一部分和在第二地址输入处接收到的第二组位，并且存储由第一地址输入可访问的第一字的第二部分 在第一地址输入处接收的一组地址位和在第二地址输入处接收的第三组地址位。 第一访问模式访问第一和第二单词的第一和第二部分中的所选择的一个。 第二访问模式访问第一和第二单词中所选择的一个的第一和第二部分。

公开(公告)号：US5185859A

公开(公告)日：1993-02-09

申请号：US745642

申请日：1991-08-15

申请人： Karl M. Guttag ,  Michael Asal ,  Richard Simpson ,  Thomas Preston ,  John Sharkey

发明人： Karl M. Guttag ,  Michael Asal ,  Richard Simpson ,  Thomas Preston ,  John Sharkey

IPC分类号： G06F9/308 ,  G06F9/312 ,  G06F9/455 ,  G06T1/20

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/455 ,  G06T1/20

摘要： A graphics processor device performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal memory. A mask bus is incorporated into the device so that, for each bit of the external data word, a mask bit is present which indicates whether data from the central processing unit (CPU) is to be written to memory (unmasked) or if that bit of memory contents is to remain unaltered (masked). The CPU data is written into a latch at the memory interface during such time as the latch is isolated from the external memory bus and during the read portion of the read-modify-write cycle. For those bits which are to be masked, the latch is overwritten with the data read from memory, while for the unmasked bits the latch remains isolated from the external memory bus. During the write portion of the read-modify-write cycle, the contents of the latch are driven onto the external memory bus. The bit-by-bit masking may also be done for data in internal memory, by multiplexing the CPU data and the internal memory data onto the CPU data bus.

摘要翻译： 图形处理器设备通过对外部或内部存储器的读取 - 修改 - 写入周期来执行中央处理单元外的逐位屏蔽。 屏蔽总线被并入设备中，使得对于外部数据字的每个位，存在一个掩码位，指示来自中央处理单元（CPU）的数据是否被写入存储器（未屏蔽），或者如果该位 的内存内容将保持不变（屏蔽）。 在锁存器与外部存储器总线隔离并且在读取 - 修改 - 写入周期的读取部分期间，CPU数据被写入存储器接口中的锁存器。 对于要被屏蔽的位，锁存器被从存储器读取的数据覆盖，而对于未屏蔽的位，锁存器与外部存储器总线隔离。 在读 - 修改 - 写周期的写入部分期间，锁存器的内容被驱动到外部存储器总线上。 通过将CPU数据和内部存储器数据复用到CPU数据总线上，也可以对内部存储器中的数据进行逐位屏蔽。

公开(公告)号：US5056041A

公开(公告)日：1991-10-08

申请号：US387404

申请日：1989-07-31

申请人： Karl M. Guttag ,  Michael Asal ,  Richard Simpson ,  Thomas Preston ,  John Sharkey

发明人： Karl M. Guttag ,  Michael Asal ,  Richard Simpson ,  Thomas Preston ,  John Sharkey

IPC分类号： G06F9/308 ,  G06F9/312 ,  G06T1/20

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30087 ,  G06T1/20

摘要： A graphics processor device is disclosed which performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal memory. A mask bus is incorporated into the device so that, for each bit of the external data word, a mask bit is present which indicates whether data from the central processing unit (CPU) is to be written to memory (unmasked) or if that bit of memory contents is to remain unaltered (masked). The CPU data is written into a latch at the memory interface during such time as the latch is isolated from the external memory bus and during the read portion of the read-modify-write cycle. For those bits which are to be masked, the latch is overwritten with the data read from memory, while for the unmasked bits the latch remains isolated from the external memory bus. During the write portion of the read-modify-write cycle, the contents of the latch are driven onto the external memory bus. The bit-by-bit masking may also be done for data in internal memory, by multiplexing the CPU data and the internal memory data onto the CPU data bus.

摘要翻译： 公开了一种图形处理器装置，其通过对外部或内部存储器的读 - 修改 - 写周期执行中央处理单元外的逐位屏蔽。 屏蔽总线被并入设备中，使得对于外部数据字的每个位，存在一个掩码位，指示来自中央处理单元（CPU）的数据是否被写入存储器（未屏蔽），或者如果该位 的内存内容将保持不变（屏蔽）。 在锁存器与外部存储器总线隔离并且在读取 - 修改 - 写入周期的读取部分期间，CPU数据被写入存储器接口中的锁存器。 对于要被屏蔽的位，锁存器被从存储器读取的数据覆盖，而对于未屏蔽的位，锁存器与外部存储器总线隔离。 在读 - 修改 - 写周期的写入部分期间，锁存器的内容被驱动到外部存储器总线上。 通过将CPU数据和内部存储器数据复用到CPU数据总线上，也可以对内部存储器中的数据进行逐位屏蔽。

公开(公告)号：US5485411A

公开(公告)日：1996-01-16

申请号：US159345

申请日：1993-11-30

申请人： Karl M. Guttag ,  Richard Simpson ,  Brendan Walsh

发明人： Karl M. Guttag ,  Richard Simpson ,  Brendan Walsh

IPC分类号： G06F7/575 ,  G06F7/38

CPC分类号： G06F7/575

摘要： A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals may employed with a multilevel logic tree circuit and a carry input to produce a bit resultant and a carry output to the next bit circuit. This structure permits formation of selected arithmetic, Boolean or mixed arithmetic and Boolean function of the three input signals based upon the current instruction. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performs a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use. The three input arithmetic logic unit (230) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is "1" only during subtraction. The carry input may be specified in the special purpose data register (D0) for certain instructions. The combination formed is optionally modified dependent upon the sign bit of one of the inputs.

摘要翻译： 三输入算术逻辑单元（230）形成三个多位输入信号的混合运算和布尔组合。 算术逻辑单元（230）首先形成布尔组合，然后形成算术组合。 当前指令驱动产生控制所形成的组合的功能信号F0-F7的指令译码器（250,245）。 三输入算术逻辑单元（230）优选地采用一组比特电路（400），每一组形成进位传播，产生和终止信号。 这些信号可以与多级逻辑树电路和进位输入一起使用，以产生位结果和进位输出到下一位电路。 该结构允许基于当前指令形成三个输入信号的所选算术，布尔或混合运算和布尔函数。 功能信号的选择使得组合对输入信号之一不敏感，从而执行剩余输入信号的两个输入功能。 指令本身可以包括功能信号和功能修改位，或者功能信号和功能修改信号可以存储在特殊数据寄存器中。 功能修改信号在使用前会引起功能信号的修改。 三输入算术逻辑单元（230）包括向最低有效位提供进位输入的最低有效位进位发生器（246）。 该进位输入由形成的组合确定，并且通常在减法期间为“1”。 某些指令可以在专用数据寄存器（D0）中指定进位输入。 根据其中一个输入的符号位可选地修改形成的组合。

公开(公告)号：US5465224A

公开(公告)日：1995-11-07

申请号：US160113

申请日：1993-11-30

申请人： Karl M. Guttag ,  Richard Simpson ,  Brendan Walsh

发明人： Karl M. Guttag ,  Richard Simpson ,  Brendan Walsh

IPC分类号： G06F7/509 ,  G06F7/527 ,  G06F7/53 ,  G06F7/575 ,  G06F12/08 ,  G06T1/20 ,  G06T11/00 ,  G06F7/38

CPC分类号： G06F7/575

摘要： A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The arithmetic logic unit (230) includes a first three input Boolean function generator (496) forming a Boolean combination F1(A,B,C), a second three input Boolean function generator (497) forming a Boolean combination F2(A,B,C), and an adder (495) forming the sum of the two Boolean combinations. The first Boolean combination F1(A,B,C) and the second Boolean combination F2(A,B,C) are independently selected from the set of all possible Boolean combinations of three multibit input signals A, B and C. The adder (495) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is "1" only during subtraction.

摘要翻译： 三输入算术逻辑单元（230）形成三个多位输入信号的混合运算和布尔组合。 算术逻辑单元（230）首先形成布尔组合，然后形成算术组合。 当前指令驱动产生控制所形成的组合的功能信号F0-F7的指令译码器（250,245）。 算术逻辑单元（230）包括形成布尔组合F1（A，B，C）的第一三输入布尔函数发生器（496），形成布尔组合F2（A，B，C）的第二三输入布尔函数发生器 ，C）和形成两个布尔组合之和的加法器（495）。 第一布尔组合F1（A，B，C）和第二布尔组合F2（A，B，C）从三个多位输入信号A，B和C的所有可能布尔组合的集合中独立地选择。加法器 495）包括向最低有效位提供进位输入的最低有效位进位发生器（246）。 该进位输入由形成的组合确定，并且通常在减法期间为“1”。

公开(公告)号：US20120145767A1

公开(公告)日：2012-06-14

申请号：US12964916

申请日：2010-12-10

申请人： Sachin Shah ,  Richard Simpson

发明人： Sachin Shah ,  Richard Simpson

IPC分类号： A61B17/068 ,  A61B17/32

CPC分类号： A61B17/07207 ,  A61B17/07292 ,  A61B2017/00477 ,  A61B2017/00951 ,  A61B2017/07214

摘要： A surgical buttress for use with a surgical stapling apparatus having a first jaw in the form of an anvil assembly and a second jaw configured to selectively receive a staple cartridge assembly. The surgical buttress includes a first body portion and a second body portion. The first body portion substantially overlies a portion of a plurality of fastener slots of the staple cartridge assembly. The staple cartridge assembly is removably operably couplable to the second jaw of the surgical stapling apparatus. The second body portion extends from the first body portion and is configured and dimensioned to be removably positioned to substantially overlie a portion of a plurality of fastener pockets of the anvil assembly of the surgical stapling apparatus when the staple cartridge assembly is operably coupled to the second jaw of the surgical stapling apparatus.

摘要翻译： 一种与外科缝合装置一起使用的手术支撑件，其具有砧座组件形式的第一钳口和被配置为选择性地容纳钉仓组件的第二钳口。 手术支撑体包括第一主体部分和第二主体部分。 第一主体部分基本上覆盖在钉仓组件的多个紧固件槽的一部分上。 钉仓组件可移除地可操作地联接到外科缝合装置的第二钳口。 第二主体部分从第一主体部分延伸并且被构造和尺寸设计成可拆卸地定位成基本覆盖在外科缝合装置的砧座组件的多个紧固件凹部的一部分上，当钉仓组件可操作地联接到第二主体部分 手术吻合装置的颚。