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1.发明授权Graphics systems, palettes and methods with combined video and shift clock control 失效图形系统，调色板和具有组合视频和移位时钟控制的方法
公开(公告)号：US5287100A
公开(公告)日：1994-02-15
申请号：US545424
申请日：1990-06-27
申请人： Karl M. Guttag , Jeffrey L. Nye , Jerry R. Van Aken , Carrell R. Killebrew, Jr. , Michael D. Asal
发明人： Karl M. Guttag , Jeffrey L. Nye , Jerry R. Van Aken , Carrell R. Killebrew, Jr. , Michael D. Asal
CPC分类号： G09G5/363 , G09G5/06 , G09G5/12 , G09G5/39 , G09G2330/12 , G09G2360/02 , G09G2360/123 , G09G5/022
摘要： An integrated circuit for use with a plurality of clock oscillators. The integrated circuit has a semiconductor chip, function performing circuitry fabricated on the semiconductor chip and responsive to clock pulses provided thereto, and a semiconductor chip package having pins connected to the function performing circuitry. The integrated circuit further has a register accessible via the pins for external entry of clock control information. A clock control circuit responsive to the clock control information entered in said register has inputs connected to pins for the clock oscillators. The function performing circuitry is connected to the clock control circuit so that clock pulses are provided to the function performing circuitry by the clock control circuit in accordance with the clock control information entered in the register. Other integrated circuits, palette devices, computer graphics systems, printer systems and methods are also disclosed.
摘要翻译： 一种用于多个时钟振荡器的集成电路。 集成电路具有半导体芯片，功能执行电路，其制造在半导体芯片上并响应提供给其的时钟脉冲，以及具有连接到功能执行电路的引脚的半导体芯片封装。 集成电路还具有可通过引脚访问的寄存器，用于外部输入时钟控制信息。 响应于在所述寄存器中输入的时钟控制信息的时钟控制电路具有连接到时钟振荡器的引脚的输入。 功能执行电路连接到时钟控制电路，使得时钟脉冲根据输入到寄存器中的时钟控制信息由时钟控制电路提供给功能执行电路。 还公开了其他集成电路，调色板装置，计算机图形系统，打印机系统和方法。
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2.发明授权Packed bus selection of multiple pixel depths in palette devices, systems and methods 失效在调色板设备，系统和方法中的多个像素深度的压缩总线选择
公开(公告)号：US5327159A
公开(公告)日：1994-07-05
申请号：US116301
申请日：1993-09-03
CPC分类号： G09G5/06
摘要： A palette device controllable by a digital computer with a video memory having a bus for supplying multiple color codes for the palette device in each bus cycle. The palette device includes a multiple-bit input for entry of the color codes from the bus, and a look-up table memory for supplying color data words in response to the color codes from the input. Color code transfer circuitry is connected between the input and the look-up table memory to supply the look-up table memory from the input sequentially with color codes of selectable width packing the entire width of the bus. Improved palette devices, graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.
摘要翻译： 可由具有视频存储器的数字计算机控制的调色板装置，其具有用于在每个总线周期中为调色板装置提供多个颜色代码的总线。 调色板装置包括用于从总线输入颜色代码的多位输入，以及用于响应于来自输入的颜色代码提供彩色数据字的查找表存储器。 颜色代码传输电路连接在输入和查找表存储器之间，以从输入中顺序地提供查找表存储器，其颜色代码可选择宽度包装总线的整个宽度。 还公开了改进的调色板设备，图形计算机系统，传真系统，打印机系统和其他系统和方法。
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公开(公告)号：US06232955B1
公开(公告)日：2001-05-15
申请号：US08080735
申请日：1993-06-22
IPC分类号： G09G128
CPC分类号： G09G5/06
摘要： A palette device controllable by a digital computer with a video memory to produce signals representing color for a video monitor. The palette device includes a multiple-bit input latch for entry of color codes from the video memory, and a look-up table memory for supplying color data words in response to color codes from the input latch. A digital to analog converter responds to color data words to produce an analog color signal. Selection circuitry connected to the input latch and to the look-up table memory supplies the digital to analog converter either with a color data word supplied by the look-up table memory or with a color data word comprised of color codes from the input latch. Improved graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.
摘要翻译： 由具有视频存储器的数字计算机控制的调色板装置，以产生表示视频监视器的颜色的信号。 调色板装置包括用于从视频存储器输入颜色代码的多位输入锁存器和用于响应于来自输入锁存器的颜色代码提供彩色数据字的查找表存储器。 数模转换器响应颜色数据字以产生模拟彩色信号。 连接到输入锁存器和查找表存储器的选择电路为数模转换器提供由查找表存储器提供的彩色数据字或与由输入锁存器组成的色码组成的彩色数据字。 还公开了改进的图形计算机系统，传真系统，打印机系统和其他系统和方法。
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公开(公告)号：US5162784A
公开(公告)日：1992-11-10
申请号：US522409
申请日：1990-05-10
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to enhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译： 本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。 第一数据寄存器存储一组X和Y坐标。 在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。 然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。 第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。 预定的颜色代码优选地存储在另一个数据寄存器中。 通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。 在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。 该指令用于提高在位映射显示中绘制线或计算曲线的速度。
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公开(公告)号：US5317333A
公开(公告)日：1994-05-31
申请号：US916302
申请日：1992-07-17
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译： 本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。 第一数据寄存器存储一组X和Y坐标。 在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。 然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。 第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。 预定的颜色代码优选地存储在另一个数据寄存器中。 通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。 在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。 该指令用于提高在位映射显示中绘制线或计算曲线的速度。
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公开(公告)号：US5249266A
公开(公告)日：1993-09-28
申请号：US865003
申请日：1992-04-08
申请人： Thomas A. Dye , Derek Roskell , Richard Simpson , Michael D. Asal , Karl M. Guttag , Neil Tebbutt , Jerry R. Van Aken
发明人： Thomas A. Dye , Derek Roskell , Richard Simpson , Michael D. Asal , Karl M. Guttag , Neil Tebbutt , Jerry R. Van Aken
CPC分类号： G06F9/30043 , G06F9/455 , G06T1/20
摘要： A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user. Similarly, responsive instead to a load command, a routine is executed which presents the series of addresses to the memory bus and loads the internal registers with the data values presented on the memory bus. The load feature is similarly utilized by the user's loading of the addressed memory locations with the desired contents of the internal registers. A system containing a microprocessor constructed according to the invention may be configured so that the emulate enable signal is generated by the control signals generated by the microprocessor upon each instruction fetch from the external memory.
摘要翻译： 一种特别适用于图形处理应用的微处理器，其具有自我仿真功能，通过该自动仿真功能，内部寄存器的内容可以在逐个指令的基础上被转储或从外部存储器加载到外部存储器。 微处理器具有对仿真使能信号或预定指令代码作出响应的电路，使得在离子的末端停止正常执行，执行跳转到预定向量。 响应于转储信号，微处理器开始执行程序，其结合存储器总线内部的寄存器内容，在存储器总线上呈现预定的一系列存储器地址。 因此，连接到存储器总线的存储器件的寻址位置可以用寄存器内容写入，以供用户的后续询问。 类似地，响应于负载命令，执行向存储器总线提供一系列地址的例程，并且使用存储器总线上呈现的数据值加载内部寄存器。 负载特征类似地由用户使用内部寄存器的期望内容加载寻址的存储器位置。 可以配置包含根据本发明构造的微处理器的系统，使得在从外部存储器提取每次指令时由微处理器产生的控制信号产生仿真使能信号。
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公开(公告)号：US5923340A
公开(公告)日：1999-07-13
申请号：US485540
申请日：1995-06-07
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may by simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译： 本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。 第一数据寄存器存储一组X和Y坐标。 在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。 然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。 第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。 预定的颜色代码优选地存储在另一个数据寄存器中。 通过适当选择存储在第二数据寄存器中的X和Y坐标数据，X或Y坐标可以单独改变，或者两者可以同时改变。 在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。 该指令用于提高在位映射显示中绘制线或计算曲线的速度。
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8.发明授权Graphics computer system, a graphics system arrangement, a display system, a graphics processor and a method of processing graphic data 失效图形计算机系统，图形系统布置，显示系统，图形处理器和处理图形数据的方法
公开(公告)号：US5437011A
公开(公告)日：1995-07-25
申请号：US191885
申请日：1994-02-04
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored In a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first data register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may be simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented or decremented. This instruction serves to enhance the speed at which a line or computed curve may be drawn in the bit mapped display.
摘要翻译： 本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。 第一数据寄存器存储一组X和Y坐标。 在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。 然后，存储在第一数据寄存器中的X和Y坐标通过添加存储在第二数据寄存器中的X和Y坐标来提前。 第二实施例是类似的，除了存储在第一数据寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。 预定的颜色代码优选地存储在另一个数据寄存器中。 通过对存储在第二数据寄存器中的X和Y坐标数据的适当选择，可以单独改变X或Y坐标，或者可以同时改变两者。 在第二个寄存器中提供有符号的X和Y坐标值可使X或Y坐标值递增或递减。 该指令用于增强在位映射显示中绘制线或计算曲线的速度。
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公开(公告)号：US5371517A
公开(公告)日：1994-12-06
申请号：US791757
申请日：1991-11-08
申请人： Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
发明人： Louis Izzi , William R. Krenik , Henry T. Yung , Chenwei J. Yin , Carrell R. Killebrew, Jr. , Karl Guttag , Jerry R. Van Aken , Jeffrey Nye , Richard Simpson , Mike Asal
CPC分类号： G06F11/006 , G09G5/06 , G09G5/18
摘要： A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.
摘要翻译： 响应于在控制数据终端接收的主时钟选择控制字，调色板从在时钟输入端接收的多个时钟信号中选择主时钟。 A电路根据主时钟的选择的分频比形成多个分频的下降时钟信号。 电路响应于在控制数据端子处接收的输出时钟选择控制字的至少一些位，从分频的下降时钟信号中选择移位时钟。 电路响应于消隐数据选择性地启用和禁用移位时钟。 响应于输出时钟选择控制字的至少一些位，电路从分频的下降时钟信号中选择视频时钟。 电路将彩色码输入端子接收的彩色码的多位字与主时钟同步。 响应于接收到颜色代码的每个多个位字，A电路输出至少一个存储器调用地址。 电路将颜色数据字存储在具有相关联的存储器调用地址的多个数据存储位置中，并且在接收到相关联的存储器调用地址时输出彩色数据字。 电路将彩色数据字选择性地写入这些多个位置。 电路将视频控制终端接收的视频控制信号与主时钟同步，并提供消隐数据。 电路选择所述颜色数据字和在所述颜色代码输入端接收的真彩色数据字之间的输出。
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10.发明授权Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive or 失效迭代划分装置，系统和方法采用最左侧的检测，最左侧的检测与排他或
公开(公告)号：US5644524A
公开(公告)日：1997-07-01
申请号：US160120
申请日：1993-11-30
CPC分类号： G06F7/74 , G06F7/535 , G06F2207/5353 , G06F7/49936
摘要： This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator in left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations of the division is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. If this is nonzero, then the numerator shifts this number of places and the corresponding quotient bits are set to "0". Next the division technique calculates the difference between the N most significant bits of the numerator and the divisor. If the difference is greater than or equal to zero, then the next quotient bit is "1". If the difference is less than zero, then the next quotient bit is "0". The difference is substituted for the N most significant bits of the numerator, if this difference was greater than or equal to zero. Then the numerator is left shifted one place. These iterations repeat until the number of iterations exceeds N. Then the quotient is completely formed and the data of the last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are "0". Using pre- and post-processing this technique can be used with signed numbers. In the preferred embodiment of this invention, the division logic is embodied in at least one digital image/graphics processor as a part of a multiprocessor formed in a single integrated circuit used in image processing.
摘要翻译： 本发明是用于划分的迭代技术。 除数具有N位，分子具有大于N位，通常为2N位。 每个迭代包括对分子的N个最高有效位的最左一位（1011,1035）的位置的初始检测。 如果该L不为零，则左移中的分子移动了L个位置（1016,1033），下一个L乘数位被设置为零，并且除法的完成迭代次数增加了L.替代实施例检测位 分子和除数的N个最高有效位的最左边的一个的最左边的位置。 如果这是非零的，则分子移动这个位数，相应的商位被设置为“0”。 接下来，分割技术计算分子的N个最高有效位与除数之间的差。 如果差值大于或等于零，则下一个商位为“1”。 如果差值小于零，则下一个商位为“0”。 如果该差值大于或等于零，则该差值代替分子的N个最高有效位。 然后分子左移一个位置。 这些迭代重复，直到迭代次数超过N.然后商完全形成，最后一个分子的数据是除法的剩余部分。 这种技术消除了这种技术确定商位为“0”的情况下的无用数据操作。 使用前处理和后处理可以使用带有签名的数字。 在本发明的优选实施例中，分割逻辑体现在至少一个数字图像/图形处理器中，作为在图像处理中使用的单个集成电路中形成的多处理器的一部分。
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