公开(公告)号：US6114219A

公开(公告)日：2000-09-05

申请号：US929865

申请日：1997-09-15

申请人： Thomas E. Spikes, Jr. ,  Sey-Ping Sun ,  Robert Dawson

发明人： Thomas E. Spikes, Jr. ,  Sey-Ping Sun ,  Robert Dawson

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion of the trench is filled with a flowable oxide-generating material which is then formed into an oxide layer. An optional dielectric layer can be deposited over the oxide layer. A portion of the oxide layer and/or the optional dielectric layer is removed to generate a substantially planer surface.

摘要翻译： 用于制造具有沟槽隔离区域的半导体器件的方法包括在衬底中形成至少一个沟槽以限定一个或多个隔离区域。 沟槽的至少一部分填充有可流动的氧化物生成材料，然后将其形成为氧化物层。 可以在氧化物层上沉积可选的介电层。 去除氧化物层和/或可选介电层的一部分以产生基本上平的表面。

公开(公告)号：US6074904A

公开(公告)日：2000-06-13

申请号：US63796

申请日：1998-04-21

申请人： Thomas E. Spikes, Jr. ,  Mark W. Michael ,  Mark I. Gardner ,  Robert Dawson

发明人： Thomas E. Spikes, Jr. ,  Mark W. Michael ,  Mark I. Gardner ,  Robert Dawson

IPC分类号： H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/76237

摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel region. One of the first pair of source/drain regions is proximal to one of the second pair of source/drain regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. An isolation trench is formed through the proximal source/drain regions and the trench is filled with a trench dielectric material such that the proximal source/drain regions are electrically isolated whereby the first transistor is electrically isolated from the second transistor.

摘要翻译： 一种用于隔离半导体器件的方法，包括提供半导体衬底。 半导体衬底包括在第一沟道区的任一侧上的第一对源/漏区和在第二沟道区的任一侧上的第二对源极/漏极区。 第一对源极/漏极区域中的一个靠近第二对源极/漏极区域中的一个。 第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。 通过近端源极/漏极区域形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得近端源极/漏极区域被电隔离，由此第一晶体管与第二晶体管电隔离。

公开(公告)号：US20110218072A1

公开(公告)日：2011-09-08

申请号：US13035683

申请日：2011-02-25

申请人： Charles B. Lohr ,  John W. Sherrill ,  Brad P. Pohl ,  Robert Dawson ,  Corey Pew

发明人： Charles B. Lohr ,  John W. Sherrill ,  Brad P. Pohl ,  Robert Dawson ,  Corey Pew

IPC分类号： F16H15/50

CPC分类号： F16H15/50 ,  F16H15/28 ,  F16H15/40 ,  F16H15/503

摘要： Inventive embodiments are directed to components, subassemblies, systems, and/or methods for infinitely variable transmissions (IVT). In one embodiment, a control system is adapted to facilitate a change in the ratio of an IVT. In another embodiment, a control system includes a carrier member configured to have a number of radially offset slots. Various inventive carrier members and carrier drivers can be used to facilitate shifting the ratio of an IVT. In some embodiments, the traction planet assemblies include planet axles configured to cooperate with the carrier members. In one embodiment, the carrier member is configured to rotate and apply a skew condition to each of the planet axles. In some embodiments, a carrier member is operably coupled to a carrier driver. In some embodiments, the carrier member is configured to couple to a source of rotational power. Among other things, shift control interfaces for an IVT are disclosed.

摘要翻译： 发明实施例涉及用于无级变速器（IVT）的部件，子组件，系统和/或方法。 在一个实施例中，控制系统适于促进IVT比例的变化。 在另一个实施例中，控制系统包括构造成具有多个径向偏移槽的承载构件。 可以使用各种本发明的载体构件和载体驱动器来促进IVT的比例的移动。 在一些实施例中，牵引行星架组件包括构造成与承载构件配合的行星轴。 在一个实施例中，承载构件被构造成旋转并向每个行星轮应用偏斜状态。 在一些实施例中，载体构件可操作地联接到载体驱动器。 在一些实施例中，载体构件被配置成耦合到旋转动力源。 其中，公开了用于IVT的换档控制接口。

公开(公告)号：US07481911B2

公开(公告)日：2009-01-27

申请号：US10520501

申请日：2003-06-27

申请人： Graham Hodgson ,  Robert Dawson

发明人： Graham Hodgson ,  Robert Dawson

IPC分类号： C25B9/02 ,  C25B9/00 ,  C25B1/24

CPC分类号： C25B1/245 ,  C25B9/02

摘要： An arrangement for installing and sealing an anode within a fluorine generating electrolytic cell is described, the arrangement comprising: an anode connection member, said anode connection member (32) passing through an aperture (70) in a skirt wall (20) and being in electrical connection with a skirt wall closure member (72) wherein the skirt wall closure member is sealingly engaged with said skirt wall and is electrically insulated therefrom.

摘要翻译： 描述了一种用于安装和密封氟生成电解池中的阳极的装置，该装置包括：阳极连接构件，所述阳极连接构件（32）穿过裙壁（20）中的孔（70）并且位于 与裙壁闭合构件（72）的电连接，其中裙壁闭合构件与所述裙壁密封地接合并与其电绝缘。

公开(公告)号：US20050191225A1

公开(公告)日：2005-09-01

申请号：US10759973

申请日：2004-01-16

申请人： Richard Hogle ,  Donald Satchell ,  Robin Clough ,  Robert Dawson ,  David Gawlowski

发明人： Richard Hogle ,  Donald Satchell ,  Robin Clough ,  Robert Dawson ,  David Gawlowski

IPC分类号： B01D53/68 ,  B01D45/04 ,  B01D53/86 ,  B01J20/02 ,  B01J20/04 ,  B01J20/08 ,  C01B7/20 ,  C25B1/24 ,  C25B15/08 ,  C01B3/00 ,  C25C7/00 ,  C25D17/00

CPC分类号： B01D53/8671 ,  B01D2255/102 ,  B01D2257/108 ,  B01D2258/0216 ,  C01B7/20 ,  C25B1/245 ,  C25B15/08

摘要： Apparatus and methods useful for disposal of hydrogen generated from a fluorine generation cell are described. In one embodiment the apparatus comprises an aerosol reduction unit and a catalytic combustion unit. The catalyst in the catalytic combustion unit is maintained at a temperature such that a pilot light or electrical spark apparatus may be eliminated. Fluorine generation apparatus and methods including an aerosol reduction unit and catalytic unit are also described.

摘要翻译： 描述了用于处理由氟产生单元产生的氢气的设备和方法。 在一个实施方案中，该装置包括气溶胶还原单元和催化燃烧单元。 催化燃烧单元中的催化剂保持在可以消除引燃灯或电火花装置的温度。 还描述了包括气溶胶还原单元和催化单元的氟生成装置和方法。

公开(公告)号：US06552776B1

公开(公告)日：2003-04-22

申请号：US09183176

申请日：1998-10-30

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

IPC分类号： G03B2754

CPC分类号： G03F7/70558 ,  G03F7/70191 ,  G03F7/706

摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.

摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

公开(公告)号：US06522013B1

公开(公告)日：2003-02-18

申请号：US09136527

申请日：1998-08-19

申请人： Robert C Chen ,  Jeffrey A. Shields ,  Robert Dawson ,  Khanh Tran

发明人： Robert C Chen ,  Jeffrey A. Shields ,  Robert Dawson ,  Khanh Tran

IPC分类号： H01L2348

CPC分类号： H01L21/76805 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Punch-through vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an exposed upper surface of a lower metal feature, e.g. portions exposed by penetrating and undercutting an anti-reflective coating. A metal such as tungsten is subsequently deposited to fill the punch-through via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H2/N2 plasma to lower its resistivity. Moreover, the thickness of the anti-reflective coating can be reduced and the process window for etching the via widened.

摘要翻译： 通过最初通过化学气相沉积首先沉积薄的共形氮化钛层来填充穿通通孔，以覆盖下部金属特征的暴露的上表面，例如， 通过穿透和底切抗反射涂层暴露的部分。 随后沉积诸如钨的金属以填充穿通孔。 实施方案包括有机钛化合物如四 - 二甲基氨基钛的热分解，以及在H 2 / N 2等离子体中处理沉积的氮化钛以降低其电阻率。 此外，可以减少抗反射涂层的厚度，并且用于蚀刻通孔的工艺窗口变宽。

公开(公告)号：US06323095B1

公开(公告)日：2001-11-27

申请号：US09489178

申请日：2000-01-21

申请人： Mark W. Michael ,  Jon D. Cheek ,  Robert Dawson

发明人： Mark W. Michael ,  Jon D. Cheek ,  Robert Dawson

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/1083

摘要： A method for forming a semiconductor device is provided. The method includes providing a substrate having a gate formed thereon. A first doped region is formed in the substrate. The first doped region extends a first distance from the gate. A second doped region is formed in the substrate. The second doped region extends a second distance from the gate. The first distance is less than the second distance. A semiconductor device includes a substrate, isolation structures defined in the substrate, and a gate disposed on the substrate between adjacent isolation structures. A first doped region is defined in the substrate proximate the gate. The first doped region extends a first distance from the gate. A second doped region is defined in the substrate proximate the gate. The second doped region extends a second distance from the gate. The first distance is less than the first distance.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括提供其上形成有栅极的基板。 在衬底中形成第一掺杂区。 第一掺杂区域从栅极延伸第一距离。 在衬底中形成第二掺杂区。 第二掺杂区域从栅极延伸第二距离。 第一距离小于第二距离。 半导体器件包括衬底，限定在衬底中的隔离结构以及设置在相邻隔离结构之间的衬底上的栅极。 在靠近栅极的衬底中限定第一掺杂区域。 第一掺杂区域从栅极延伸第一距离。 在靠近栅极的衬底中限定第二掺杂区域。 第二掺杂区域从栅极延伸第二距离。 第一距离小于第一距离。

公开(公告)号：US6156649A

公开(公告)日：2000-12-05

申请号：US60434

申请日：1998-04-14

申请人： Fred N. Hause ,  Robert Dawson ,  Charles E. May

发明人： Fred N. Hause ,  Robert Dawson ,  Charles E. May

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： A semiconductor process in which a first silicide is formed on silicon upper surfaces upon which a second silicide is selectively deposited. A refractory metal is blanket deposited on a semiconductor substrate. The semiconductor substrate is then heated to a first temperature to react portions of the refractory metal above the exposed silicon surfaces to form a first phase of a first silicide. The unreacted portions of the refractory metal then remove, typically with a wet etch process. The semiconductor substrate is then heated to a second temperature to form a second phase of the first silicide. The second temperature is typically greater than the first, and the resistivity of the second phase is less than a resistivity of the first phase. Thereafter, a second metal silicide is selectively deposited on the first silicide, preferably through the use of a chemical vapor deposition process. In one embodiment, the selectively deposited second silicide is reacted with the existing first silicide to form a composite silicide structure exhibiting uniform sheet resistivity independent of the dimensions of the underlying silicon structure.

摘要翻译： 一种半导体工艺，其中第一硅化物形成在硅上表面上，在其上选择性地沉积第二硅化物。 难熔金属被覆盖在半导体衬底上。 然后将半导体衬底加热至第一温度，以使暴露的硅表面上方的难熔金属的部分反应，以形成第一硅化物的第一相。 难熔金属的未反应部分通常用湿蚀刻工艺除去。 然后将半导体衬底加热至第二温度以形成第一硅化物的第二相。 第二温度通常大于第一温度，第二相的电阻率小于第一相的电阻率。 此后，优选通过使用化学气相沉积工艺，在第一硅化物上选择性地沉积第二金属硅化物。 在一个实施例中，选择性沉积的第二硅化物与现有的第一硅化物反应以形成独立于下面的硅结构的尺寸的均匀的薄层电阻的复合硅化物结构。

公开(公告)号：US6104064A

公开(公告)日：2000-08-15

申请号：US306508

申请日：1999-05-06

申请人： Daniel Kadosh ,  Mark I. Gardner ,  Michael Duane ,  Jon D. Cheek ,  Fred N. Hause ,  Robert Dawson ,  Brad T. Moore

发明人： Daniel Kadosh ,  Mark I. Gardner ,  Michael Duane ,  Jon D. Cheek ,  Fred N. Hause ,  Robert Dawson ,  Brad T. Moore

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L29/66659 ,  H01L29/7835

摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

摘要翻译： 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。