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公开(公告)号：US20120161255A1
公开(公告)日：2012-06-28
申请号：US12979592
申请日：2010-12-28
CPC分类号： B81C1/00293 , B81C2203/0145
摘要： Embodiments of the invention provide methods of sealing a micro electromechanical systems (MEMS) cavity and devices resulting therefrom. A first aspect of the invention provides a method of sealing a micro electromechanical systems (MEMS) cavity in a substrate, the method comprising: forming in a substrate a cavity filled with a sacrificial material; forming a lid over the cavity; forming at least one vent hole over the lid extending to the cavity; removing the sacrificial material from the cavity; depositing a first material onto the lid such that a size of at least one vent hole at a surface of the substrate is reduced but not sealed; and depositing a second material onto the first material to seal the at least one vent hole, wherein a MEMS cavity within the substrate and beneath the at least one vent hole substantially retains a pressure at which the at least one vent hole is sealed by the second material.
摘要翻译： 本发明的实施例提供了密封微机电系统（MEMS）腔和由此产生的装置的方法。 本发明的第一方面提供了一种密封衬底中的微机电系统（MEMS）空腔的方法，所述方法包括：在衬底中形成填充有牺牲材料的腔体; 在空腔上形成盖子; 在所述盖上形成延伸到所述空腔的至少一个通气孔; 从腔中去除牺牲材料; 将第一材料沉积到所述盖上，使得所述基板的表面处的至少一个通气孔的尺寸减小但不被密封; 以及将第二材料沉积到所述第一材料上以密封所述至少一个通气孔，其中所述基底内的MEMS空腔和所述至少一个通气孔下方基本上保持所述至少一个通气孔被所述第二通气孔密封的压力 材料。
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公开(公告)号：US20130207235A1
公开(公告)日：2013-08-15
申请号：US13371605
申请日：2012-02-13
申请人： Margaret A. Faucher , Paula M. Fisher , Thomas H. Gabert , Joseph P. Hasselbach , Qizhi Liu , Glenn C. MacDougall
发明人： Margaret A. Faucher , Paula M. Fisher , Thomas H. Gabert , Joseph P. Hasselbach , Qizhi Liu , Glenn C. MacDougall
IPC分类号： H01L21/331 , H01L29/73 , B82Y99/00
CPC分类号： H01L29/732 , H01L21/76221 , H01L29/0649 , H01L29/0804 , H01L29/1004 , H01L29/161 , H01L29/66234 , H01L29/66242 , H01L29/66272 , H01L29/737 , H01L29/7371
摘要： Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
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公开(公告)号：US08932931B2
公开(公告)日：2015-01-13
申请号：US13371605
申请日：2012-02-13
申请人： Margaret A. Faucher , Paula M. Fisher , Thomas H. Gabert , Joseph P. Hasselbach , Qizhi Liu , Glenn C. MacDougall
发明人： Margaret A. Faucher , Paula M. Fisher , Thomas H. Gabert , Joseph P. Hasselbach , Qizhi Liu , Glenn C. MacDougall
IPC分类号： H01L21/331 , H01L29/66
CPC分类号： H01L29/732 , H01L21/76221 , H01L29/0649 , H01L29/0804 , H01L29/1004 , H01L29/161 , H01L29/66234 , H01L29/66242 , H01L29/66272 , H01L29/737 , H01L29/7371
摘要： Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
摘要翻译： 本发明的方面提供了形成双极结型晶体管的方法。 该方法包括：在发射台上设置包括均匀的氮化硅层的半导体衬底，以及在发射极底座下面的基底层; 在基区的第一端和第二端应用光掩模; 以及用所述光掩模进行氮化硅蚀刻以同时形成与所述发射极基座相邻的氮化硅间隔体，并暴露所述双极结型晶体管的基极区域。 氮化硅蚀刻可以是端点蚀刻。
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公开(公告)号：US08138008B1
公开(公告)日：2012-03-20
申请号：US12955224
申请日：2010-11-29
IPC分类号： H01L21/00
CPC分类号： B81C1/00666 , B81B2203/0118 , B81C1/00111
摘要： Solutions for forming a semiconductor including an oxide MEMS beam are disclosed. In one embodiment, a method of forming a beam within a sealed cavity includes: depositing a lower insulator layer comprising one or more layers; depositing an upper insulator layer over the first insulator layer, the upper insulator layer comprising one or more layers, wherein a composite stress of the upper insulator layer is different than a composite stress of the lower insulator layer.
摘要翻译： 公开了用于形成包括氧化物MEMS光束的半导体的解决方案。 在一个实施例中，在密封空腔内形成梁的方法包括：沉积包括一层或多层的下绝缘体层; 在所述第一绝缘体层上沉积上绝缘体层，所述上绝缘体层包括一层或多层，其中所述上绝缘体层的复合应力不同于所述下绝缘体层的复合应力。
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公开(公告)号：US20120133006A1
公开(公告)日：2012-05-31
申请号：US12955220
申请日：2010-11-29
IPC分类号： H01L29/84
CPC分类号： H01G5/18 , B81B3/0072 , B81B2203/0118 , B81C2201/0167 , H01G5/16
摘要： In one embodiment, a semiconductor structure includes a beam positioned within a sealed cavity, the beam including: an upper insulator layer including one or more layers; and a lower insulator layer including one or more layers, wherein a composite stress of the upper insulator layer is different than a composite stress of the lower insulator layer, such that the beam bends.
摘要翻译： 在一个实施例中，半导体结构包括位于密封空腔内的光束，所述光束包括：包括一层或多层的上绝缘体层; 以及包括一层或多层的下绝缘体层，其中上绝缘体层的复合应力不同于下绝缘体层的复合应力，使得光束弯曲。
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6.发明授权Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics 有权局部定制化学机械抛光（CMP）抛光率的电介质公开(公告)号：US08637403B2
公开(公告)日：2014-01-28
申请号：US13323093
申请日：2011-12-12
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31053 , H01L21/3105 , H01L21/31155 , H01L21/76819 , H01L21/76823 , H01L21/76825 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.
摘要翻译： 制造半导体结构的方法包括通过选择性地改变绝缘体膜的碳含量来改变绝缘体膜的局部化学机械抛光（CMP）研磨速率。
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