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33 条记录 (耗时 0.021 秒)

    Voltage generator with superimposed reference voltage and deactivation signals
    6.
    发明授权
    Voltage generator with superimposed reference voltage and deactivation signals 有权
    具有叠加参考电压和去激活信号的电压发生器

    公开(公告)号：US06285176B1

    公开(公告)日：2001-09-04

    申请号：US09693778

    申请日：2000-10-20

    申请人： Thilo Marx ,  Torsten Partsch ,  Thomas Hein ,  Patrick Heyne

    发明人： Thilo Marx ,  Torsten Partsch ,  Thomas Hein ,  Patrick Heyne

    IPC分类号： G05F316

    CPC分类号： G05F1/465

    摘要： A voltage generator configuration includes a voltage generator which generates a second voltage from a first voltage using a reference voltage and which can be deactivated by using a deactivation signal. The voltage generator configuration is distinguished in that the deactivation signal is fed to the voltage generator over a line through which the reference voltage is also fed to the voltage generator.

    摘要翻译： 电压发生器配置包括电压发生器，该电压发生器使用参考电压从第一电压产生第二电压，并且可以通过使用去激活信号来去激活。 电压发生器配置的区别在于，去激活信号通过一个线路馈送到电压发生器，通过该线路，参考电压也被馈送到电压发生器。

    Synchronous integrated memory
    7.
    发明授权
    Synchronous integrated memory 失效
    同步集成存储器

    公开(公告)号：US06259652B1

    公开(公告)日：2001-07-10

    申请号：US09624448

    申请日：2000-07-24

    申请人： Patrick Heyne ,  Thomas Hein ,  Torsten Partsch ,  Thilo Marx

    发明人： Patrick Heyne ,  Thomas Hein ,  Torsten Partsch ,  Thilo Marx

    IPC分类号： G11C700

    CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066

    摘要： Data items D1, D2 read from memory cells MC are simultaneously buffer-stored in memory stages Si of a FIFO memory MEM and are read out again simultaneously from said FIFO memory at a later point in time. Output units OC1, OC2 serve for outputting, at a data output P, the first data D1 synchronously with positive edges of an external clock signal CLK and the second data D2 synchronously with negative edges of the external clock signal CLK.

    摘要翻译： 从存储器单元MC读取的数据项D1，D2同时被缓冲存储在FIFO存储器MEM的存储级Si中，并且在稍后的时间点再次从所述FIFO存储器读出。 输出单元OC1，OC2用于在数据输出端P以与外部时钟信号CLK的负沿同步地与外部时钟信号CLK和第二数据D2的正边沿同步地输出第一数据D1。

    Delay locked loop for generating complementary clock signals
    8.
    发明授权
    Delay locked loop for generating complementary clock signals 有权
    用于产生互补时钟信号的延迟锁定环

    公开(公告)号：US06661265B2

    公开(公告)日：2003-12-09

    申请号：US10178251

    申请日：2002-06-24

    申请人： Torsten Partsch ,  Thilo Marx ,  Patrick Heyne ,  Thomas Hein

    发明人： Torsten Partsch ,  Thilo Marx ,  Patrick Heyne ,  Thomas Hein

    IPC分类号： H03L706

    CPC分类号： H03K5/151 ,  H03K5/133 ,  H03K2005/00039 ,  H03K2005/00195 ,  H03L7/0812

    摘要： A delay locked loop has a delay unit with a delay time that can be controlled in a manner dependent on a control signal. In order to generate complementary delayed clock signals, provision is made of switching elements, which tap off the clock signal to be delayed along the series circuit of delay elements. Each of the delay elements has a series circuit of two inverters. One of the delayed clock signals is tapped off in each case at the output of the second of the inverters of the delay elements, and the complementary output signal from the delayed output signals is tapped off at the first of the inverters. What is thus made possible is that, disregarding the frequency of the clock signal to be delayed and the length of the delay time, the complementary delayed clock signals always have the same phase angle with respect to one another.

    摘要翻译： 延迟锁定环路具有可以以取决于控制信号的方式来控制延迟时间的延迟单元。 为了产生互补的延迟时钟信号，提供开关元件，其切断时钟信号以沿着延迟元件的串联电路被延迟。 每个延迟元件具有两个逆变器的串联电路。 在延迟元件的第二反相器的输出处，在每种情况下，延迟时钟信号中的一个被分接，并且来自延迟的输出信号的互补输出信号在第一逆变器处被分接。 因此，如果不考虑要延迟的时钟信号的频率和延迟时间的长度，互补延迟的时钟信号总是相对于彼此具有相同的相位角。

    Current mirror circuit
    9.
    发明授权
    Current mirror circuit 有权

    公开(公告)号：US06657422B2

    公开(公告)日：2003-12-02

    申请号：US10033877

    申请日：2001-12-27

    申请人： Patrick Heyne ,  Thilo Marx ,  Thomas Hein ,  Torsten Partsch

    发明人： Patrick Heyne ,  Thilo Marx ,  Thomas Hein ,  Torsten Partsch

    IPC分类号： G05F320

    CPC分类号： G05F3/262

    摘要： A current mirror circuit has an input path, which has a current source and, connected in series therewith, a first transistor circuit with at least two transistors, wherein one of the transistors can be connected in parallel with the other of the transistors. In an output path, which has a second transistor circuit with at least two transistors, one of the transistors can be connected in parallel with the other of the transistors. The control terminals of the transistors of the first and second transistor circuits can be connected to the input path. As a result, the current mirror circuit can be changed over between two operating modes with a different current requirement with comparatively short changeover times.