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    Integrated memory, and a method of operating an integrated memory
    5.
    发明授权
    Integrated memory, and a method of operating an integrated memory 失效
    集成存储器以及操作集成存储器的方法

    公开(公告)号：US06882554B2

    公开(公告)日：2005-04-19

    申请号：US10287501

    申请日：2002-11-04

    申请人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    发明人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    IPC分类号： G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06

    CPC分类号： G11C7/067 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/105

    摘要： An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

    摘要翻译： 集成存储器具有用于激活读/写放大器的行线，列线和列选择线。 在每种情况下，一组预定数量的存储单元属于行和列地址。 此外，存储器具有对应于预定数量的多个连接焊盘。 一组存储器单元中的每个存储器单元与一个连接焊盘相关联。 设计用于控制存储器访问的控制电路，并且可以操作该控制电路，使得通过列地址激活至少两个不同的列选择线。 对于两个或更多列地址，其中一列列选择行被激活。 因此，可以减小存储芯片上的延迟时间和线路长度。

    Control circuit for an S-DRAM
    6.
    发明授权
    Control circuit for an S-DRAM 有权
    用于S-DRAM的控制电路

    公开(公告)号：US06717886B2

    公开(公告)日：2004-04-06

    申请号：US10248874

    申请日：2003-02-26

    申请人： Acharya Pramod ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier ,  Christian Weis

    发明人： Acharya Pramod ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/4076

    摘要： Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.

    摘要翻译： 用于由具有用于存储等待时间值的可编程模式寄存器的由高频时钟信号计时的S-DRAM的数据路径的控制电路; 延迟发生器，用于以可切换的等待时间延迟由内部序列控制器产生的数据路径控制信号; 延迟解码器，其以取决于存储在模式寄存器中的等待时间值的方式切换等待时间发生器，由至少一个信号延迟元件提供，其可由等待时间解码器切换并用于信号延迟 具有特定延迟时间的数据路径控制信号，如果存储的等待时间值高，延迟解码器切换相关联的信号延迟元件。

    Method and circuit arrangement for controlling write access to a semiconductor memory
    7.
    发明授权
    Method and circuit arrangement for controlling write access to a semiconductor memory 有权
    用于控制对半导体存储器的写访问的方法和电路装置

    公开(公告)号：US07224625B2

    公开(公告)日：2007-05-29

    申请号：US11117698

    申请日：2005-04-29

    申请人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier ,  Christian Weis

    发明人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier ,  Christian Weis

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1027 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229

    摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

    摘要翻译： 本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动， 要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存 ，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。 本发明还涉及一种用于执行该方法的电路装置。

    Method and circuit arrangement for controlling write access to a semiconductor memory
    8.
    发明申请
    Method and circuit arrangement for controlling write access to a semiconductor memory 有权
    用于控制对半导体存储器的写访问的方法和电路装置

    公开(公告)号：US20050254307A1

    公开(公告)日：2005-11-17

    申请号：US11117698

    申请日：2005-04-29

    申请人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier ,  Christian Weis

    发明人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier ,  Christian Weis

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4096

    CPC分类号： G11C7/22 ,  G11C7/1027 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229

    摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

    摘要翻译： 本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动， 要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存 ，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。 本发明还涉及一种用于执行该方法的电路装置。

    Synchronous integrated memory
    10.
    发明授权
    Synchronous integrated memory 有权
    同步集成存储器

    公开(公告)号：US06275445B1

    公开(公告)日：2001-08-14

    申请号：US09617649

    申请日：2000-07-17

    申请人： Stefan Dietrich ,  Peter Schrögmeier ,  Torsten Partsch ,  Christian Weis

    发明人： Stefan Dietrich ,  Peter Schrögmeier ,  Torsten Partsch ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1078

    摘要： A memory has data lines through which data connections are connected to groups of memory cells via a synchronizing unit. The synchronizing unit is disposed adjacent to the cell group and has a clock input to which an internal clock signal is fed. In the event of a write access to the memory, the synchronizing unit synchronizes with the internal clock signal data signals that are fed via the data connections and are synchronous with an external clock signal.

    摘要翻译： 存储器具有数据线，数据连接经由同步单元连接到存储器单元组。 同步单元被布置成与单元组相邻并且具有被馈送内部时钟信号的时钟输入。 在对存储器进行写访问的情况下，同步单元与经由数据连接馈送的内部时钟信号数据信号同步，并与外部时钟信号同步。